Designing emerging chips requires advanced methods and flows, which include the utilization of IP blocks and interoperable EDA tools.
There was an interesting panel discussion at this week’s Design Automation and Test in Europe (DATE) Conference that included representatives from various links in the SoC supply chain – EDA suppliers, IP providers, services companies and even a bona fide SoC developer. The panelists were asked to provide their view of where the EDA and IP industries were headed. Like the proverbial blind men who are asked to describe what is in front of them by touching different parts of an elephant, everyone brought a slightly different perspective to the table.
But not as different as you might think. Interestingly, five of the six panelists focused the majority of their talk on IP. For good reason: IP, and more generally design reuse, is the crux of SoC’s future and value proposition. Everyone agrees that the ability to quickly and efficiently re-use silicon-proven functionality in new designs holds the key to addressing the technical complexity, time pressures and jaw-dropping economics of bringing new SoCs to market. There simply is no other way.
So it’s no wonder everyone is jumping on the IP bandwagon. With headlines like ARM’s market valuation reaching $12 billion, and Semico reporting the third-party IP market grew by close to 22 percent last year, it’s a legitimate growth strategy for any type of company in the ecosystem. This generated considerable discussion on who is best qualified to be the providers of IP in the long term.
What wasn’t so clear from this panel is how we are going to take advantage of the incredible potential of IP and design reuse. I mean, what is it really going to take to assemble and integrate all of it together, deal with both hardware and software on a SoC platform, and ensure it’s ready to hand off to the implementation phase?
While the idea of plug-and-play sounds great on PowerPoint slides, there are a whole lot of methodology and tool capabilities that are still missing to make it as automated and efficient as other parts of the design process. This is where the rubber meets the road.
Like building a house and starting the discussion talking about the bricks, most of the panelists were talking about the need for quality IP and standards, how we can grow the market for innovative applications by developing more IP, and even where the IP business model might end up. Perhaps as part of a foundry offering? Merged more completely with traditional EDA suppliers, like Synopsys and Cadence? All legitimate issues, questions to be addressed and great panel fodder.
But there was very little discussion on the methodologies and tools required to manage, assemble and integrate all this great IP to realize SoCs. In my mind this is the real elephant in the room. Then again, maybe it’s the blind guy at the other end of the elephant.
Perhaps this was because no one wants a continuation of the current ‘EDA classic’ tool model into SoC Realization. I believe as a result the large EDA companies talked about IP almost exclusively because of the attraction of the IP business model. Can’t say I find fault in their desire to get a higher IP-ish multiple.