DFI Technical Group releases latest high-speed memory controller and PHY interface specification that enables transition to next-generation DDR4 memory
I just heard from the DDR PHY Interface (DFI) Technical Group today that it has released the preliminary DFI 3.0 specification, the latest version of the industry specification that defines an interface protocol between DDR memory controllers and PHYs.
The new specification aims to help with the development of chips to support the emerging DDR4 memory standard. It was developed by group members, which included representatives from ARM Limited, Cadence Design Systems, Inc., Intel Corporation, LSI Corporation, Samsung Electronics, ST-Ericsson and Synopsys, Inc. The Technical Group reports that the DFI interface is in use by hundreds of companies with 3100 downloads to date.
The DFI 3.0 specification lays out the methods for interfacing to DDR4 devices with proposed data rates up to 3.2 Gbits/second per pin -- more than 50 percent faster than the current DDR3 standard -- and extends the low-power interface that was introduced with DFI 2.1. By accounting for frequency and power challenges at high speeds, the new specification aims to ensure exceptional performance in systems using DDR4 memory.
To get a look a the spec, head here to download at www.ddr-phy.org.