The slowdown in the pace of Moore's Law, the emerging importance of the SoC and the rapid growth of the mobile market all tend to favor an open, plug-and-play foundry and design ecosystem.
The main battle on the CPU front is between Intel/x86 and ARM architecture. While Intel historically has had the upper hand in performance, ARM-designed cores have delivered superior performance/watt.
To effectively compete against ARM, Intel will need to design its low-power Atom cores in the most power efficient way possible. To design a true low power core, Intel may need to decouple the Atom from legacy x86-based architecture and develop a new ground-up design that delivers highly competitive performance/watt. Intel will also have to be in aggressive catch-up mode as it tries to reverse the momentum of an already large, established and robust ARM software ecosystem.
In the initial years of the PC era, as x86 became the predominant CPU architecture, an entire ecosystem of application software was spawned that was designed to run solely on x86. This effectively precluded or seriously hindered competing architectures like PowerPC from ever gaining a foothold in the marketplace.
Analogously, in the present day, ARM architecture is significantly further along in achieving critical mass in the mobile SoC space. The prevalence of ARM in a range of post-PC devices from smartphones and tablets (90% market share) to televisions and cars have placed ARM in a commanding position to inhibit the newer Intel Atom architecture from achieving traction. Practically speaking, for Intel to gain a meaningful share in the mobile market, it now has to ensure compatibility with the ARM software ecosystem.
This will force Intel to compete on price which will limit how much revenue it can eventually generate. This is a dynamic that Intel has not had to face in the PC segment.
Battlefront #3 – Silicon/foundry technology
Intel’s ability to make the best performing transistor at the highest possible yields and volumes is unparalleled. This capability served it immensely well in the closed ecosystem when Intel was essentially competing against itself in the quest to make a better transistor. In the closed ecosystem, performance trumped power and design flexibility and high ASPs ensured that development cost was not a significant limiter.
In the open ecosystem, however, the ability to integrate disparate functional accelerators in the most power-efficient and cost-effective manner is paramount.
As an example, Samsung can make the highly successful and functional A5 processor for Apple using a trailing edge 45nm transistor process and integrate all the complex IP blocks from a variety of vendors while keeping the ASP under $20. Samsung’s minimum metal pitch at the 45nm node is comparable to that of Intel at the more advanced 32nm node, yet the cost of a 32/28nm wafer is much higher than that of a 45nm wafer. Even with a trailing edge transistor, Samsung can offer best-in-class area density and best-in-class power efficiency at an acceptable performance point. Furthermore, chip companies like Apple or Qualcomm usually prefer to use a standard process which enables portability of designs between foundries which in turn mitigates supply issues while driving down cost.
Radical deviations from foundry standard processing will only serve to increase the adoption barrier in an open silicon ecosystem. If tri-gate becomes a challenge for foundries to adopt quickly (owing to sheer cost, complexity and innovation needed), it may further strengthen the manufacturing and design ecosystem around a planar architecture.
Part 1 of this article highlighted the emerging importance of the mobile SoC and its impact on the industry landscape and the continued evolution of Moore’s Law. The success metrics in the new landscape are not just higher transistor performance but higher system functionality, lower system cost and lower power.
Part 2 discussed why the new landscape favors an open foundry and design ecosystem.
Based on the above discussion and judgment, the following trends are likely to define the semiconductor industry over the next decade.
1. The 28nm node will have at least a five-year lifecycle. Foundries will innovate to enhance power/performance/cost and extend the life of the 28nm transistor. Poly-Si gate technology is likely to enjoy a renaissance at the 28nm node as it offers the lowest cost and lowest risk option for mobile products and platforms that do not require the highest performance.
2. A longer 28nm lifecycle will provide more time to develop a 20nm technology that will also benefit from enhancements at the 28nm node. The 20nm node will see universal adoption of the metal gate-last scheme which in turn may promote design portability and potentially level the playing field among the foundries. The 20nm node will also see a long lifecycle (at least 5 years) given a hitherto unclear patterning roadmap to the 14nm node.
3. Intel will extend its tri-gate leadership beyond the 22nm node and will continue to dominate the CPU/server segment (single thread / high performance), albeit with increasing competition from the ARM ecosystem. The next five years will see the emergence of ARM based servers – HP/Calxeda, NVIDIA, Applied Micro and Marvell have all announced plans to introduce ARM based server products. Using an open ecosystem with customizable IP will enable significant cost and power reduction for these new entrants.
4. Intel has a significant power advantage at the transistor level, but not being part of an open ecosystem may hinder its efforts to gain mobile market share at the system level. Recent announcements indicate that after decades of blindly following Intel, former archrival AMD is retooling with an emphasis on the SoC to enable a plug-and-play approach and win in the mobile space. AMD plans to continue using x86-based architecture while also being open to licensing-in ARM cores if needed. AMD is thus responding to the changing landscape by entertaining both an x86-based architecture and the open ecosystem.
5. In a power and cost competitive environment, Lego-block on-chip integration of hardware accelerators (modem, CPU, graphics, etc.) will prove to be extremely efficient. Compared to centralized CPU/GPU cores, SoCs will be far more effective, especially in the tablet and ultra-book form-factors.
6. The headlining SoC duel in the coming year will be between Intel’s 22nm tri-gate mobile SoC (Silvermont, 2013) and Qualcomm/TSMC’s 28nm planar mobile SoC (Snapdragon S4, 2012). This will provide a direct match-up between the planar/trailing transistor versus the non-planar/leading transistor.
7. A move to 450mm wafer size has the potential to disrupt the industry cost model. A glut of fully depreciated 300mm fab infrastructure and ongoing uncertainty in the EUV tooling roadmap will make it a difficult value proposition at least in the foreseeable future.
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(1) Viewpoint: How will the chip wars be won -- Part 1
-- Pushkar Ranade is director of process integration at SuVolta,
Inc. Prior to joining SuVolta in 2010, Ranade was with Intel Corporation
where he contributed to transistor process integration and development
of Intel’s 65nm, 45nm and 22nm logic technology. Ranade joined Intel in
2003 after graduating with a Ph.D. from the University of California,
Berkeley. At Berkeley, his research was in the area of sub-70nm CMOS
transistor design and involved the integration of novel gate materials
and ultra-shallow junctions. The opinions expressed here are his
alone,and do not reflect those of EE Times.