Much of the wishful thinking around 3-D packaging technology, hyped by commodity memory manufacturers, can be attributed to the old adage that "those who do not learn from history shall be compelled to re-live it."
While we're on the topic of price, consider the most compelling argument against MCM: margin. The chip maker of the KGD apps processor can reasonably expect 50 percent margin. If he is asked to build an MCM that stacks DRAM and flash KGD with his apps processor, once he combines these KGD, can he expect to extract 50 percent margin for the DRAM and flash he's put together with his apps processor? I don't think so. Furthermore, the chip maker building the MCM needs this margin because of greater risk he incurs building the MCM. Each time a packaged part fails final test, he's out not only his apps processor but whatever he spent acquiring the DRAM and flash.
Another consideration is the supply chain for the individual parts comprising the MCM. When a system customer buys an apps processor, he negotiates a contract price that typically goes over the life of the end product. This results because the system manufacturer's engineering team buys the apps processor because it represents a superior feature set for its system product. And, the team is not likely to change until a competitor comes up with a better option, which will typically come with a different pin configuration and requiring a new board layout.
Contrast this supply chain with that of DRAM and flash, purchased by buyers looking to minimize cost on a commodity product. The contracts are short term with a range of prices that allow the buyer to benefit from over supply or cut his losses should the price rise. Furthermore, the buyer always has the option to buy memory components on the spot market to further save cost. By combining memory on board with the apps processor, this price leverage for the system manufacturer goes away.
If you have any doubts, just research DRAM chip pricing and availability for single die chips versus stacked die DRAM. If the companies that sell at a small loss and make it up in volume have such a high price on stacked die, what are the odds of the more sane and profitable ASSP suppliers integrating memory KGD stacked with their SoCs? Low!
There is also the challenge of taking away the system resellers ability to upsell customers on memory upgrades. Only system suppliers with extremely high channeling clout or own channels can dictate a few configurations and insist the customers love them.
Not to mention the technical challenges that memory die have very different thermal specifications than logic SoCs. Stacked silicon die are bound to present thermal challenges beyond ones solved to date.
Finally, the KGD is not attractive to semiconductor manufacturers in general. Chip suppliers must develop a new business model to ship KGD instead of packaged parts, which means his added expense and a distraction from core business. For KGD to be attractive to a chip supplier, the volume of KGD must be huge and the business must be seen as long term, not a flash in the pan that will be overwhelmed when some enterprising physicists discovers how to legitimize reboot Moore's Law for yet another decade.
If memory companies really want to become profitable and break the seldom boom many bust cycle they need to innovate beyond lowest common denominator designed in committee products. Hoping that complex packaging cost adders is a way out of product commoditization is just bad business planning.
Andre Hassan is director of field applications for non-volatile memory intellectual property provider Kilopass Technology Inc.
Someone had better clue IBM to the hype factor. IBM Fellow Dr. Subramanian Iyer was showing cross sections of 32nm chips with 11 layers of metal, deep-trench capacitors for eDRAM, and TSVs at the recent GSA Silicon Summit. Mr. Hassan's article repeats all of the same arguments used more than 20 years ago to explain why surface-mount technology was doomed: can't rework the boards with a soldering iron, can't test the boards with through-hole testers, JTAG costs too much to add to chips, blah, blah, blah. That dismal prediction of failure seems to have been wrong.
There are too many technical advantages and too few disadvantages at this point for 3D IC assembly not to take off. Rather than labeling technical analyses as "hype" and "wishful thinking," how about a more fact-based argument to counter the technical advantages and the obvious, displayed progress by companies such as IBM and Xilinx?
The Raspberry Pi board uses a standard Broadcom BCM2835 SoC with POP (package-on-package)mounted DRAM. Nevertheless, every mobile phone handset out there already uses a 3D IC stack with wirebonding and has for years. So we're just talking a difference in interconnect here, as well as deciding who is responsible for and gets paid for a working 3D stack.
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This is an interesting analysis, but I have to say its more than the memory guys waiving the 3-D IC flag these days.
It's big logic and fab folks like Altera, IBM, Qualcomm, TSMC, Xilinx and others. Are they all drinking the Kool-Aid?
"..But alas, today's module is tomorrow's much lower cost IC. ..".
So true in the past but the 3D proponents are just hoping that Moores's Law will finally grind down if not for device fundamentals ( leakage ) then at least for lithography ( EUV ) or just the min. order size needed to justify a $ 10 billon Fab
I see most of the KGD work happening at the IDMs and most of the 3d packaging happening in conjunction with the packaging houses. The package (and sometimes test) houses will pretty much follow whatever the IDM's push but most packaging houses that I've seen don't really have much advanced test technology. This is likely to change as some of the bigger boys (like AMD) go more fabless. And to address another point, there is speed testing done at wafer level, particularly by captive processor module companies who don't want to throw away expensive chips. But alas, today's module is tomorrow's much lower cost IC.