Editor's note: This article was rewritten in rebutal to comments made in April by Mark Bohr, an Intel Senior Fellow. As reported by EE Times, Bohr said the fabless-foundry model is"collapsing."
What are the problems?
1. Parametric yields at 28 nm are not at expected levels. Process variables such as random dopant fluctuations, line width and line gap variations, and via resistance, which affect RC-related timing issues, result in both unpredictable and low parametric yields for the targeted specifications. The process variables have increasing impact on leakage, power consumption and yields.
A perspective on the challenges facing foundry vendors and fabless companies is shown in the following figure.
Click on image to enlarge.
To address the chasm problem areas, an IDM-type interface is required between process teams at the foundry vendors and design teams at the fabless companies.
Large fabless companies and foundry vendors have the financial resources to set up the required interfaces and collaborate on resolving problems. Smaller companies will face financial challenges.
A key issue is who establishes and pays for these IDM-type disciplines? Fabless company, foundry, or both? It is likely that many of the costs and disciplines will need to be shared.2. Increasing capex requirements for being a leader in the foundry business.
TSMC’s CAPEX in 2012 is $8 billion, which at $1 billion per 10,000 wafers, gives additional capacity of 80,000 wafers per month at 28 nm and 20 nm. Samsung’s nonmemory capex is also likely to be $8 billion in 2012 ($6.5 billion announced), which will give an additional 80,000 wafers per month as well. Globalfoundries is ramping output from its Malta fab and building capacity to 30,000 wafers per month in 2012 in addition to the 80,000 wafers per month already in Dresden. UMC’s capex in 2012 is $2 billion, but the company has announced that Fab 12 will receive $8 billion in funding. UMC will likely need a funding partner in order to invest the $8 billion in the near term.
Only a small number of companies will be able to invest the required capex for large wafer capacity through the 14-nm technology node. Fabless companies will, however, need to select which foundry vendor partner they collaborate with.
3. Higher process complexity as feature dimensions shrink.
A major problem for IDMs as well as foundry vendors is that the cost of developing advanced processes increases as feature dimensions shrink, a perspective of which is shown below.
Click on image to enlarge.
The cost for 20 nm is based on bulk CMOS, and 14 nm is based on FinFET (it is understood that Intel is using FinFET at 22-nm). The cost of developing the FinFET process is between $2 billion and $3 billion for the leaders and will be $1.8 billion for close followers. With R&D at 10 percent of revenues, revenues will need to be $9 billion, with process technology development over two years. Having the appropriate wafer processing and wafer fab facilities at 14 nm will cost more than $5 billion for 40,000 wafers per month.
The migration to 450-mm will require an investment of $10 billion for 40K wafers per month, with revenue potential of $10 billion per year. The only participants will be those with access to large financial resources, but payback can be good for foundry vendors that establish appropriate business models.
It is a high-risk, high-reward environment. If foundry/fabless companies establish an IDM-type interface, there is no reason that they cannot be as effective as an IDM.