Are you an engineer with a sense of humor or interested in developing one? Volunteer to be among a small, esteemed panel of your peers chosen by me as an EE Life Monthly Caption Contest Judge.
Here’s how to apply: Right after March 31, read all the comments on the March Caption Contest where the entries are still ballooning. As you read each caption, notice the level to which you are moved to smile, chuckle or belly laugh. Mark the captions that gave you the biggest eruptions of humor. Then send to me (email@example.com) your top three, noting their rank order.
Here’s where the serious work comes in. I want you to include a sentence or two on why your top pick tickled your funny bone. For extra credit, give me a sentence or two about you. For instance, you could tell me the funniest engineering-related April Fools joke or prank you know. (By the way, this is not an April Fools prank, I want help judging the contest!)
April will be our test run. As the Exalted Leader of EE Life, I will determine which of the candidates are seated on the official EE Life Caption Contest Panel for May.
The compensation comes in two parts. You will experience the honor of being among the few of your peers chosen to enter the pantheon of EE Life judges with all the rewards that confers for your LinkedIn resume. You also will get a new source of humor likely to ease your stress and improve your quality of life. So don’t wait—start laughing today.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.