Late last month, I spoke with Chris Loberg, senior marketing manager at Tektronix, about how PCI and PCI Express (PCIe) are influencing testing. As PCI/PCIe standards have evolved, they have increased in scalability and improved throughput. In April, the PCIe Gen 3 spec was formally tested by the PCI SIG. Loberg called that "a big landmark for this very venerable serial bus."
What's next for PCIe? Loberg sees the industry at a crossroads. The consumer electronics industry is dealing with the impending demise of the personal computer for individual use. The marketshare for tablets, mobiles, and smart devices is growing. PCIe is right in this sweet spot. Loberg said the PCI SIG continues to move forward, developing Gen 4 (it's very early in the development process), doubling the data rate to 16Gbit/s, and making an effort to consider energy conservation. On the other hand, his wish list includes more emphasis on the role that the PCIe bus plays on a mobile platform.
Right now, M-PHY is being used as the physical mechanism for PCIe, but a variant called MEX or Mobile PCIe is also being developed. As a result, we see the PCI SIG driving the development (it just held a conference last week), but the MIPI Alliance is working to revise/review the interplay with M-PHY. By way of background, M-PHY is a high-speed serial PHY interface from the MIPI Alliance to JEDEC, USB-IF®, and PCI-SIG®.
All this is very interesting, but how is test and measurement affected? There are really two sides to the testing story here: compliance from the consumer side (items need to plug together and work) and conformance testing (making sure the devices are within specifications). Loberg said the challenge for many is that there's a specification for M-PHY, but it's much looser than what people are used to for the PCIe specs. For instance, the M-PHY spec gives reference levels but doesn't specify how to set up automated testing of your device. That's the area where test and measurement companies are stepping up their efforts to assist.
What do you think? Is PCIe at a crossroads? Does it have to declare itself for mobile (lower power) or performance (higher throughput)? Have you encountered testing challenges with these specs? What do you need from the test and measurement industry in this area?
- How to test for MIPI PHY compliance
- Compliance testing from PCI SIG