Timing constraints are well explained in this tool-agnostic book on Synopsys Design Constraints.
I have just finished reading the book Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC) written by Sridhar Gangadharan of Atrenta and Sanjay Churiwala of Xilinx. They also had help from Frederic Revenu, who wrote a chapter on the Xilinx extensions to SDC.
Before I go any further I have to admit that I have never written a design constraint in my life, so I came at this book as someone who understood the problem but had never been involved with solving it. Back when I was doing design, we hardly even used a simulator let alone half of the tools that are available today.
The book is very well structured and reads easily. Each chapter takes on a subject and develops it well. Even though I have never written constraints, I was able to follow along at each step, and the small examples they provided were helpful to me in understanding the lessons. The book is also completely tool-generic. The authors make no attempt to sell you on any particular tool, and you could read the book and not know that it came from an EDA company.
If I have one complaint about this book: A chapter is missing. At several points in the book, the authors discuss how certain constraints are estimated or that information is not available until a certain point in the flow. They also explain how static timing can be useful at certain points in the flow for ascertaining different types of timing checks.
While I understand that every company uses different tools and flows, I would have liked to see a chapter that explained the writing and evolution of constraints during the design process. What things should companies focus on at certain points in the flow? When should the constraints be updated? When should static timing be run? What useful information will it provide? This could have also included a larger, more typical example, and while I understand that the constraints files can become very large, it would have been helpful to look at something a designer may face. The actual constraints files could have been made available online and small parts of it described in the chapter.
These comments, however, do not detract from the book. I highly recommend this book to anyone who needs to get acquainted with timing constraints. I feel that I could start writing them myself after reading this book. A content list is provided below:
- Synthesis Basics
- Timing Analysis and Constraints
- SDC Extensions through TCL
- Generated Clocks
- Clock Groups
- Other Clock Characteristics
- Port Delays
- Completing Port Constraints
- False Paths
- Multi-Cycle Paths
- Combinational Paths
- Modal Analysis
- Managing your Constraints
- Miscellaneous SDC Commands
- XDC: Xilinx Extensions to SDC
At 253 pages, the book lists at $119. More information can be found on the Springer site and the book is available slightly cheaper on Amazon. In the future, I hope to bring you an excerpt of this book, which would appear on my EDN blog -- Practical Chip Design.
I would love to hear other people's opinions of this book, especially from those who have written design constraints in the past.
ó Brian Bailey -- keeping you covered