Brian Bailey's weekly roundup of news and activities associated with EDA and IP.
This is a roundup of news and activities associated with EDA and IP over the past week in a condensed format that is quick to read.
X-FAB Silicon Foundries has a new A/MS Reference Kit supporting advanced methodology for analog/mixed-signal design. The Kit enables rapid adoption of constraint-driven design, mixed-signal simulation, floorplanning, schematic-driven layout, automated routing, timing-driven digital block implementation, and signoff. It is based on the latest mixed-signal flow from Cadence Design Systems. The Kit includes an OpenAccess PDK to enable mixed-signal designs for 180nm and other technologies, a reference design, flow scripts, and detail documentation for easy setup and fast adoption.
Algotochip has announced that Nitto Denko, a $7 billion Japanese company, has increased its investment, making them a primary investor in Algotochip. While the Algotochip Bluebox can be used to support any SoC, ASIC, or FPGA design, the company plans to help potential customers by providing foundry-ready C-code for technologies like Advanced LTE, Smart Grid, multimedia applications, and other communications markets. Nitto Denko is a diversified materials manufacturer specializing in sheets, films and other materials that utilize technologies such as polymer synthesis, adhesion, and coating.
Cypress Semiconductor has added some new components for PSoC Creator 2.2, the integrated design environment (IDE) for Cypress's PSoC 3, PSoC 4, and PSoC 5LP programmable system-on-chip architectures. The Component Pack 6 update includes four new PSoC Components -- pre-verified "virtual chips" represented by an icon -- that users can drag-and-drop into a design. The four components are: a software transmit UART, emulated EEPROM, Segment/Matrix LED driver, and SC/CT Comparator.
TSMC has expanded its collaboration with Cadence on the Virtuoso custom and analog design platform to design and verify its own IP. Additionally, TSMC has extended its native SKILL-based process design kits (PDKs) portfolio for the 16nm FinFET process, creating and delivering qualified native SKILL-based PDKs.
IAR Systems has a new version of its embedded development tool chain IAR Embedded Workbench for AVR32 -- 4.20. The version includes enhancements to the code optimizations technology, gaining significantly faster code execution as well as smaller code size. The enhancements result in more than 80 percent higher scores compared with the previous version on the CoreMark benchmark test suite. New functionality includes a new text editor with auto-completion, parameter hints, code folding, block select and indent, bracket matching, zoom, and word/paragraph navigation. A new source browser adds features for going directly to a chosen declaration, and for finding all references to a symbol. The inline assembler has been extended and project connections are introduced to use external device configuration tools alongside IAR Embedded Workbench.
IAR has also announced support for the new Vybrid F series controller solutions available from Freescale Semiconductor. Full support for the Vybrid VF3xx, VF5xx, and VF6xx product families are provided using the development tool suite IAR Embedded Workbench for ARM.
SEMI forecasts semiconductor equipment sales will reach $43.98 billion in 2014, a 21 percent increase over estimated 2013 equipment spending according to the mid-year edition of the SEMI Capital Equipment Forecast. Some of the increase is due to significant NAND flash fab investments by Samsung in China and Toshiba/Sandisk in Japan, and investments by Intel, including its fabs in Ireland. The forecast indicates that next year will be the second largest spending year ever, surpassed only by $47.7 billion spent in 2000.
Cadence has introduced a new approach to custom design with its Virtuoso Layout Suite for Electrically Aware Design (EAD). This in-design electrical verification capability enables design teams to monitor electrical issues while a layout is created, rather than wait until the layout is completed before verifying that it meets the original design intent. Engineers can electrically analyze, simulate and verify interconnect decisions in real time, resulting in layout that is electrically correct-by-construction. This real-time visibility lets engineers reduce conservative design practices -- or "over-design" -- that can negatively impact a chip's performance and area. Cadence believes that it can reduce the design cycle by up to 30 percent.
CEA-Leti and EV Group have launched a three-year common lab to optimize temporary- and permanent-bonding technologies related to 3D TSV integration and all direct bonding heterostructures. This collaboration targets results that will make 3D TSV integration more efficient and cost effective, and open new areas of wafer bonding with covalent bonding at room temperature.