I recently had the opportunity to interview Eric Starkloff, engineer and senior VP of marketing at National Instruments. Here are the highlights of his responses when I asked him how test has changed, and if he had any funny stories from his career.
I recently had the opportunity to interview Eric Starkloff, engineer and senior VP of marketing at National Instruments. Here are the highlights of his responses when I asked him about how test has changed, and if he had any funny stories from his career. (To find out more about Eric, and for the text of our entire interview, see my article on EDN.com)
EE Times: What are the next challenges for the T&M industry?
Eric Starkloff (ES): I do believe we are facing some major disruptions. It starts with cost of test. The devices we are testing are getting more complex, and yet, the cost to produce them is decreasing -- both consequences of Moore’s Law. Despite this, test hasn’t kept pace, and therefore continues to be a larger portion of the cost to invent and produce new technology. This has to change, and I believe software-defined modular systems, which also benefit from Moore’s Law, are fundamental to bending this cost curve.
EE Times: How has the role of the test engineer changed?
ES: First, test engineers have to become more proficient in software development as test systems have become more and more software centric. They have also have to learn new technologies at an increased pace. Take wireless test, for example. This used to be the domain of the specialist -- we all know a guru microwave engineer. But, as wireless has permeated nearly every device, more and more test engineers have had to also learn to test wireless among numerous other functions on their device under test.
EE Times: Any funny stories?
ES: Here’s one that stays on topic: During my research project in school, we had just gotten our first ASIC back. We spent around $100k for the fab and received around 20 chips to test. We put one down on a test board I designed and were all excited to see a year’s worth of work come to fruition. Unfortunately, it didn’t work -- we got all garbage data.
We spent several days trying other chips from the lot, debugging at the board level, and using a probing station for diagnosing the chip. We hit a lot of dead-ends and were very frustrated. I was sitting around a table brainstorming with the team and staring at the PCB when I noticed a stub of a trace on the top level of the board that didn’t look right. Sure enough, it was an error in the layout tool and caused a short. It just happened to be on the top layer of a multi-layer board, so we literally took an Exacto knife to it, cut out the stub, and voila! -- everything worked. The lesson: Creativity and persistence are a must, but nothing beats dumb luck!
What do you think are the major test challenges today? Are you finding cost of test to be prohibitive?