3D ICs gathered support among chip, equipment, and materials vendors at last week's Semicon West event.
SAN FRANCISCO — Semicon West showed the equipment and material sector is clearly leading the way in proliferating 2.5 and 3D ICs. The event demonstrated previously rare or hesitant supporters have grown in numbers, see the value of this alternative compared to CMOS scaling, and are determined to make it successful.
As manager of the 3D IC working group in the Global Semiconductor Alliance from 2008 to 2011, I learned the importance of cooperation across the entire semiconductor ecosystem. I also learned to be patient, because market acceptance of this powerful technology has been very slow so far.
The technology gained momentum at Semicon. For instance, more than 100 attendees expressed a high level of interest at a workshop hosted by Suss that had a surprisingly heavy emphasis on 2.5/3D.
I already knew Suss has been investing in the development of 2.5/3D manufacturing equipment for several years. I learned recently one of its major customers is getting ready for volume production with a number of its bonders/de-bonders.
Market researchers at Yole said Apple, Qualcomm, Sony, and several others are investing significantly in 2.5/3D technology. A new Yole report shows Amkor, Hynix, IBM, Intel, Micron/Elpida, Samsung, Stats ChipPac, TSMC, and Taiwan's ITRI are in the lead in filing 3D patents. However, still high costs of through-silicon vias are delaying market introductions, the market researchers said.
The technology is progressing well in key areas of design, manufacturing, reliability, and logistics, said Ron Huemoeller, senior vice president for advanced technologies at Amkor. Only issues around the business case still delay the rollout of 2.5/3D ICs, he said.
Vern Styger, a product manager at Asahi Glass, outlined how glass interposers address today's cost challenges. He showed how glass can be used in wafer form and as panels and eventually as rolls to lower cost.
A representative of Brewer Science compared technical and cost tradeoffs of three de-bonding mechanisms. A product manager from Suss detailed bonders, de-bonders, and cleaners for wafers from 100 to just 30 microns thick and discussed a low cost, high yield de-bonding methodology.
GlobalFoundries sees major opportunities in wafer-level packaging and 2.5/3D ICs. A TSV module will become an integral part of every new process, said Jon Greenwood, the company's director of packaging R&D.
Via-middle copper TSVs will shrink from 5x50 microns, to 3x50 and then to about 2x30 microns, said Eric Beyne, scientific director and 3D expert at the IMEC research institute. The need for faster data exchange at lower power is why IMEC and its members invest heavily in 2.5/3D technology, he said.
From what I heard at Semicon, 2.5/3D technology has a good opportunity to win a significant share of the market. Indeed, I believe the IC industry will bifurcate in the near future into those pursuing Moore's Law and those pursuing "More than Moore." Which camp companies pick will be based on several criteria -- total system cost, IC cost, development costs and their amortization over production volumes, risk of failure, time to market, and, last but not least, the technical requirements of increasingly complex solutions.