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Slideshow: What's Available in LPDDR3?
7/23/2013

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Memory IP
When it comes to electronics, time to market is everything. To accelerate implementation, this controller and PHY IP from Cadence supports the development of both LPDDR2 and LPDDR3 devices. The PHY has been implemented in the TSMC 28nm high-performance mobile (HPM) process, available with attached IO pads. Features include a two-stage reordering queue to optimize bandwidth and latency, an industry-standard DFI PHY interface, and coherent bufferable write completion.
When it comes to electronics, time to market is everything. To accelerate implementation, this controller and PHY IP from Cadence supports the development of both LPDDR2 and LPDDR3 devices. The PHY has been implemented in the TSMC 28nm high-performance mobile (HPM) process, available with attached IO pads. Features include a two-stage reordering queue to optimize bandwidth and latency, an industry-standard DFI PHY interface, and coherent bufferable write completion.

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