When it comes to electronics, time to market is everything. To accelerate implementation, this controller and PHY IP from Cadence supports the development of both LPDDR2 and LPDDR3 devices. The PHY has been implemented in the TSMC 28nm high-performance mobile (HPM) process, available with attached IO pads. Features include a two-stage reordering queue to optimize bandwidth and latency, an industry-standard DFI PHY interface, and coherent bufferable write completion.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.