Mobile device users demand three things from their devices: functionality, speed, and long battery life. To address the last two needs (if not the first), JEDEC released the LPDDR3 standard, a mobile memory interface specification boasting a data rate of 1,600Mbit/s.
Now, LPDDR3 was a bit of a rush job. It was written, approved, and published in about a year and a half, and if you know anything about the standards process, you know that is nothing short of extraordinary. Nevertheless, the standard features some nifty innovations (which we discussed when it was released last year), such as write leveling and command-address training. Designers can leverage the features to improve timing queues and timing closure and ensure clear communications between the device and the system on chip.
Though it typically takes a couple of years after the release of a standard for compliant devices to reach the market, now seems like a good time to survey some LPDDR3 offerings already available.
Click the image below to begin the slideshow.
When it comes to electronics, time to market is everything. To accelerate implementation, this controller and PHY IP from Cadence supports the development of both LPDDR2 and LPDDR3 devices. The PHY has been implemented in the TSMC 28nm high-performance mobile (HPM) process, available with attached IO pads. Features include a two-stage reordering queue to optimize bandwidth and latency, an industry-standard DFI PHY interface, and coherent bufferable write completion.