Use of NAND flash memory devices has increased enormously due to their high performance, high density, and matured process capability. NAND flash memory technology continues to drive minimum feature size when compared with other memory devices and typically encounters scaling challenges before DRAM or logic.
Anticipating significant scaling difficulties in the low 1z nanometer node, researchers are investigating other emerging memory device technologies, such as spin-torque transfer MRAM, phase change RAM, and resistive RAM. From 2012 through the first quarter of this year, six companies have dominated the market.
TechInsights recently compared all the leading-edge 2x/1x nanometer NAND flash memory products, including Sandisk/Toshiba 24nm and 19nm, SK-Hynix 26nm, IM Flash Technologies (a Micron-Intel joint venture) 25nm and 20nm, and Samsung 27nm and 21nm NAND flash. Our report (registration required) describes all the process and device technologies that NAND array cells currently employ. The parameters include memory array and NAND string efficiency, well structure, self-aligned shallow trench isolation (SA-STI) and self-align process (SAP), effective floating gate (FG) height, crosstalk-related dimensions, control gate (CG) filling factors, air-gap process integration, and double patterning technology for each NAND flash memory device.
As the NAND array cell is scaled down, one key issue is FG charge loss, which causes larger threshold voltage shifts in the cell transistor. As the NAND FG scales to 10nm class, most major manufacturers will continue to use a thick FG structure combined with air-gap process technology or thin planar FG structure as a storage node, as shown below. According to a wordline/bitline half-pitch comparison, most of the devices (except the Samsung 27nm and IMFT 20nm) use the higher bitline half-pitch.
An overview of NAND storage node structure for each device. Most manufacturers use an IPD layer 12nm or thinner as devices scale down, so the physical thickness of the IPD layer is a key factor for future NAND device scaling. IMFT reduced FG height dramatically by adopting a planar structure. This reduces cell interference and increases process reliability.
IMFT's 20nm NAND device has the smallest unit cell area so far. Its 25nm device uses a lower doped P-well between a shallow P-well and deep N-well, which is likely to further reduce junction capacitance. Most manufacturers use a thinner interpoly dielectric (IPD) layer of 12nm or less as devices scale down. This means the physical thickness of the IPD layer is one key factor for future NAND device scaling. Tunnel oxide thickness scales down to 6nm on the most leading-edge NAND devices. Both CG and FG heights are also scaling down due to SA-STI and SAP difficulties. IMFT reduces FG height dramatically by adopting a planar structure that can reduce cell interference and increase process capability.
Other issues include cell-to-cell interference, IPD integrity, cell operation windows, and program disturbance. In a process view, when the FG-to-FG space is less than 20nm, a 10nm-thick IPD layer is no longer an effective barrier insulation. CG poly-Si filling in the narrow space between IPD layers is another barrier for the 10nm technology node. Defect-controlled deposition processes are needed, including micro-void elimination on the interface. For cell endurance and data retention, air-gap architecture on both FG/CG and bitline metal wiring is necessary.
A comparison of gate air-gap features on each NAND device is shown below. All the NAND manufacturers adopted an air-gap process to achieve high performance and reliability. Toshiba implemented an air-gap process on its 19nm NAND device, while Samsung adopted it on 21nm. IMFT has used a more mature air-gap process on both the wordline and bitline structure since its 25nm NAND technology.
A comparison of gate air-gap features on each NAND device. Advanced gate air-gap processes have been adopted to achieve high performance and reliability. Toshiba adopted an air-gap process on its 19nm NAND device, while Samsung adopted it on 21nm. IMFT uses a mature air-gap process adopted from its 25nm NAND devices.
As for 3D stackable NAND flash, some major NAND manufactures have already revealed their own 3D NAND architectures, such as pipe-shaped bit cost scalable combined with through silicon via technology, terabit cell array transistor and vertical gate-NAND. Most 3D NAND architectures are based on 6F2 (3F x 2F) cell size, but the gate processes and device structures are different. The bit cost can be scaled down using a 3D stackable NAND structure, but to be economical, integration of more than 32 layers is needed.
A uniform, repeatable, and well-controlled process sequence for each vertical cell transistor is a major barrier to overcome. If 3D stackable NAND flash memory process technologies are not mature enough to replace conventional or thin FG structures for the 1z nanometer technology node, manufacturers will target emerging nonvolatile memory devices to replace 2D NAND devices.