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Comparing Leading-Edge NAND Flash Memories

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JanineLove
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Air Gap
JanineLove   7/26/2013 10:43:05 AM
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How does an air-gap process to achieve high performance?

ScottenJ
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Re: Air Gap
ScottenJ   7/26/2013 12:37:38 PM
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Air gaps reduce capacitance thereby lowering parasitic coupling between adjacent cells.

ScottenJ
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Re: Air Gap
ScottenJ   7/26/2013 12:40:51 PM
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The "Our report (registration required)" link goes to a page that lists the report but doesn't have an option to download it.

 

mcgrathdylan
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Re: Air Gap
mcgrathdylan   7/26/2013 6:54:12 PM
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@ScottenJ- yes, I see what you mean. That is a little confusing. I think if you are interested in the report you need to fill out the information on the left side of the page (name, email, company, etc.). Then I'm not sure what happens.

http://www.techinsights.com/reports-and-subscriptions/open-market-reports/Report-Profile/?ReportKey=9236

JanineLove
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IPD Layer
JanineLove   7/26/2013 10:43:35 AM
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"This means the physical thickness of the IPD layer is one key factor for future NAND device scaling." What are the manufacturing challenges that need to be overcome for this?

resistion
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CEO
Re: IPD Layer
resistion   7/28/2013 11:52:27 AM
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Ultimately the space between FGs of different bit lines would be all IPD.

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