This is a roundup of news and activities associated with EDA and IP that broke over the past week.
MagnaChip Semiconductor has announced a range of intelligent sensor product families featuring 0.18 micron mixed signal & analog technology with low-power consumption. The MXsensor families target the growing market for applications ranging from smartphone, tablet, and navigation to medical devices. The MXsensor™ families include e-Compass and digital Hall sensors.
The Xilinx 7 Series GTH transceiver successfully completed testing for 10GBASE-KR LogiCORE IP at the University of New Hampshire InterOperability Laboratory (UNH-IOL) validating that it fully meets UNH-IOL’s receiver (Rx) and transmitter (Tx) electrical and protocol compliance tests for backplane applications.
This achievement enables OEMs to develop high-performance network and datacenter solutions with 10 Gigabit or 40 Gigabit backplanes that conform to the IEEE Std 802.3 using Xilinx’s 10GBASE-KR LogiCORE IP and enable 40GBASE-KR4 LogiCORE IP on Virtex®-7 XT and HT devices with GTH transceivers.
Oasys Design Systems has raised a new round of funding led by Intel Capital, Xilinx, and former Cadence CEO, Joe Costello. Funds will be used to expand the company's sales, marketing, and product development activities. Series B funding came from Intel and Xilinx in April 2012.
The OpenMP Consortium has released OpenMP 4.0. This release provides a new mechanism to describe regions of code where data and/or computation should be moved to another computing device. This extends its reach beyond pure HPC to include DSPs, real-time systems, and accelerators. OpenMP aims to provide high-level parallel language support for a wide range of applications, from automotive and aeronautics to biotech, automation, robotics, and financial analysis.
Providing designers with an important tool to validate and verify their PCI Express (PCIe) designs, Cadence Design Systems has a new SpeedBridge Adapter for PCIe 3.0. This new adapter provides easy bring-up and fast debug of PCIe-based designs when used with a Cadence Palladium Verification Computing Platform, and is backwards compatible with PCIe 2.0-, 1.1-, and 1.0a-based designs. The SpeedBridge Adapter for PCIe 3.0 provides high-speed interaction with real-world traffic in a pre-silicon environment running production-level software drivers and an OS.
Altera has a fully verified EtherCAT (Ethernet for Control Automation Technology) protocol intellectual property (IP) for Altera FPGAs. This is a collaboration between Altera, EtherCAT Technology Group (ETG), and Softing Industrial Automation GmbH, for a licensing structure that gives developers access to leading Industrial Ethernet protocols with no upfront license fees, no per-unit royalty reporting, or protracted negotiations. The solution implements both the protocol IP and software stack into an FPGA using programmable logic and a soft embedded processor.
STMicroelectronics, ARM, and Cadence have made new contributions to the SystemC Language Working Group of the Accellera Systems Initiative. The joint work includes new interfaces for interrupt modeling, APIs for register introspection that enable display and update of register values, and new approaches for memory-map modeling.
The Multicore Association has a new working group, the Software-Hardware Interface for Multi-Many Core (SHIM), which will provide a common interface to abstract the hardware properties that matter to multicore tools. The primary goal for SHIM is to define an architecture description standard useful for software design. For example, the processor cores, the inter-core communication channels, the memory system, the network-on-chip (NoC) and routing protocol, and hardware virtualization features are among the architectural features that SHIM will either directly or indirectly describe.
The DINI Group has a new Xilinx Virtex-7-based FPGA board with 56 million ASIC gates. Two boards can be seamlessly linked together for up to 112 million ASIC gates, in a new rack mount chassis that provides better cooling and ruggedness. High gate count designs operate at very high speeds. Daughter cards (up to eight per board) provide additional memory, interconnects, peripheral interfaces, and any required custom functions.