Samsung was a bit economical with the engineering details when it announced its 128Gbit multilayered NAND flash memory this week. The company did not mention how many layers are used in the device or what geometry process technology is used to make it. However, a Samsung spokesperson who responded to our email questions has allowed us to fill in some details and invoke hand-waving arguments about others.
Samsung did say in its press release that the technology can stack "as many as 24 cell layers." Through email, the company confirmed that this first vertical NAND flash memory is a 24-layered device, and that it is being manufactured at Hwaseong, South Korea.
The spokesperson would not answer questions about the manufacturing process geometry for the 128Gbit vertical NAND or whether the charge-trap technology is capable of multi-level cell (MLC) operation. But the company did say the die area is approximately the same as that for a 2D NAND flash memory made using mid-10nm-class process technology.
As far as I know, Samsung has both 64Gbit and 128Gbit 2D NAND flash memories being manufactured in 1X nm process technology. The 128Gbit 2D NAND device was announced in April. If we make a couple of assumptions, this should allow a little more light to be shed on the vertical NAND. Let us assume that the die area of the 128Gbit V-NAND flash memory is the same as for the 128Gbit 2D NAND flash introduced by Samsung April on 1X-nm class manufacturing process. Let us also assume that MLC has not been deployed in the V-NAND flash.
Since the 2D NAND used three-bit MLC memory, it follows that the V-NAND memory must have three times as many memory cells spread across 24 layers. This means that the memory cell density per layer of the V-NAND memory can be lower than that for the 2D NAND memory by a factor of eight. Area varies with the square of linear geometry. Therefore, it follows that the V-NAND could be up to about 2.8 times more relaxed in its minimum geometry than the 2D NAND.
These are coarse approximations, because parts of the V-NAND die area may be given over to additional addressing circuitry to cope with multiple layers or for through-silicon vias that might be used later for a stacked die arrangement. But putting those uncertainties to one side, if the 128Gbit 2D NAND were made using a 16nm minimum geometry manufacturing process technology, then it seems a V-NAND memory of the same capacity and die area would require only about 45nm of minimum geometry.
This jump back multiple manufacturing process generations could have significant benefits in terms of getting extended use out of amortized equipment and wafer fabs, resulting in reduced costs. Of course, there is the extra cost and yield-limiting effect of lining up and connecting 24 layers.
What is most striking and slightly worrying is that Samsung said in its press release that the technology is capable of up to 24 layers. If that remains the case, vertical NAND a la Samsung would provide a one-time benefit only.
The industry expectation is that vertical NAND can scale in terms of the number of layers and allow the industry to jump back to easier-to-produce manufacturing nodes, where more electrons are stored and cycling endurance and reliability are higher and better understood. As the first company into the market with vertical NAND, Samsung looks set to be the pathfinder for how far that vertical scaling can go.