In an IER-enabled future, circuit blocks take on an aura of silicon IP. Known-good circuits include robust descriptions, embedded component-value calculators, waveforms, and test procedures.
In my first two columns on this subject, I outlined the poor state of EDA data exchange and my conclusions about the root cause. In this column, I'll put forth a vision that the capability of standard design exchange can enable.
To briefly recap, I'm advocating a vendor-independent format for importing schematics and PCB reference designs. Reference designs are published in a variety of formats, none of which are one-click importable into common EDA tools. For the sake of discussion, I'll refer to the design exchange format as an IER file -- a play on Ohm's Law.
Let's assume we are transported to an IER-enabled future in which I'm commencing a hypothetical design for a battery-powered remote monitor and control system. The system requires an efficient battery-operated DC supply, differential instrumentation amplifiers, a processing subsystem, and a RF data communications link. The idea is similar to going to a consolidated travel site such as Orbitz or Kayak. I visit a reference design repository -- let's call it CircuitBlox.net -- and search for DC-to-DC power supplies. Circuit-specific parameters such as quiescent currents and efficiency can be entered, and up pops a listing of available circuits published in IER. Each is accompanied by a description and a link that attaches the schematic to the end of my mouse pointer, allowing me to place it on my schematic page.
In a similar manner, I research instrumentation amplifiers and other key system elements. As part of this, I find it necessary to visit device vendors known for the most power-stingy op-amps and search their reference design or application note libraries for a suitable design. I find just what I need and bring the circuit into the project. Next, I need an analog integrator, but it's been a while since I've used one. I consult the online version of Walter G. Jung's classic IC Op-Amp Cookbook, which has been republished with IER schematics. After finding the section on integrators, I simply click on the schematic, and the circuit appears at the end of the mouse pointer. The online book includes a web-based calculator that lets me calculate component values quickly. In this future world, there are a plethora of these circuit catalog books. Most are available electronically, and circuits can be imported directly via IER into any board-level schematic entry tool.
In our IER-enabled future, circuit blocks begin to take on an aura of silicon IP. Known-good circuits include robust descriptions, embedded component-value calculators, waveforms, and (when appropriate) test procedures, perhaps even JTAG vectors. Like the PDF in today's world, IER is everywhere in the board-level electronics design domain.
The processing section of my design presents a different type of situation. The system has robust processing requirements and high-speed memory. I find several suitable reference designs from device vendors' online repositories. After I import any IER-published schematics, my design tools immediately query the web, provide a total BOM cost, and even optimize the cost by sourcing components from several vendors. Though I'm not using this as a purchasing tool, the virtually effortless result provides me with BOM cost and lead-time insight early in the cycle. This is a contributing factor in my processing reference design selection.
Once I decide on the reference design for the processing subsystem, I import the PCB implementation. This allows me to leverage the signal integrity-proven layout. Once imported, the schematic and PCB are intelligently associated. This becomes the base of my project's PCB implementation.
The other schematic pages that were derived from IER circuit blocks obtained from the variety of online sources are consolidated into the project file. Reference designators are re-annotated, and key traces are locked. Peer design reviews are conducted, and the storyboarded design is forwarded to my layout colleague for placement, routing, design for test, etc.
Our team is under considerable pressure to develop a proof-of-concept prototype as part of a government project -- design and BOM optimization will come later. Prototypes arrive a week later, and now the fun really begins.
It's important to note that this IER-enabled future is not a pipe dream. I've only scratched the surface of the types of board-level circuit IP, new businesses, and levels of OEM design efficiency that could be realized. Everything mentioned could have been provided more than 15 years ago if the industry had a widely adopted, working design exchange standard. Semiconductor vendors and their distributors are missing a huge opportunity to differentiate their offerings by taking a key logical step in helping their customers utilize reference designs to reduce time to volume.
The vision put forth in this column is being forfeited because of the interests of a few EDA companies, the apathy of semiconductor device vendors, and the complacency of OEMs. Given the length of time this topic has been essentially dormant, it is not reasonable to expect the same mindset that has created this situation to usher in an electronic design data exchange revolution. To solve the problem, stakeholders will have to pursue another course of action. The status quo isn't working.
On the bright side, initiatives such as IPC-2581, while presently primarily a PCB manufacturing output format, show promise that the community is waking up and opposing the propagation of proprietary data regimes. This initiative is also noteworthy because of the cooperation among competing software companies and electronics OEMs in moving the standard forward. This spirit of cooperation will be required to address the situation I've discussed in this three-column miniseries and usher in a new level of design efficiency. As always, I welcome your comments and feedback.