Memory has emerged as a key differentiator in how embedded designers are achieving the user experience (UX) that today's consumers expect: instant on.
We live in a world where instant gratification and multitasking are the norm. We want what we want, when we want it. Consumers have come to require and expect innovative solutions that provide instant access to increasing amounts of heterogeneous information types, regardless of time, location, or device used. And if this isn’t a big enough shoe to fill, consumers also want those devices to be as stylish, small, portable, and as low power as possible.
Due to this increased focus on intelligent devices—and the network of such devices, called the Internet of Things (IoT)—semiconductor vendors and embedded developers are feeling the pressure to develop innovative products swiftly. In turn, embedded designers are feeling the pressure to choose a solution to address this wide range of design requirements to meet end-user preferences. It can be overwhelming to say the least.
A key expectation for the user experience (UX) is "instant-on" operation, and boot time is the central challenge that plays into this instant-on trend. Automotive dashboard development is a good example of where this trend is very present. But we’re also seeing instant-on affecting many other industrial and consumer applications.
Memory is critical in instant-on operation. Using compressed root-file system images to save NV memory space, for instance, and unpacking it into RAM for execution will add additional seconds to the boot process. In fact, most systems that take more than 10 seconds to boot spend the majority of that time in MCU processing of the compressed code.
Ever-changing architectures to meet desired UX
Although in some instances applications will be able to use a single memory architecture, in order for applications of 10 or 20 MB to boot in a few milliseconds high-end systems need to use a hybrid combination of flash architectures. Parallel NOR flash has emerged as a key solution for designers to provide execute-in-place (XIP) boot code in devices with modest code size that require a fast start-up, Parallel NOR flash delivers fast and secure boot, which also gives consumers a rich and interactive UX. Whether you’re looking for a standard interface, page-mode, burst or simultaneous read/write, there is a parallel NOR flash solution for your application. This type of memory can be found in automotive, consumer and mobile products including GPS, smartphones, and e-readers.
On the other hand, automotive electronics, home and industrial controls, and high performance consumer applications are using increasingly sophisticated graphical user interfaces (GUIs) that execute out of RAM to enhance and simplify the interaction between user and device. The higher-resolution images, animations, and video that result from more sophisticated GUIs in turn creates a higher demand for read throughput from the flash memory where this information is archived. At the same time, however, many of these applications need compact designs, and parallel NOR flash typically needs 40 or more pins in their address and data interface.
In these compact, high-performance applications, embedded developers are using newer Quad serial peripheral interface (SPI) NOR flash with enhancements such as double data rate (DDR) mode to satisfy the growing demand for memory density while keeping interface pin count down. With SPI NOR flash, designers have a low pin count option with the higher data rates needed for higher read throughput, increased board space, and options for more complex designs. With DDR, the rate for copying data into RAM increases substantially, up to 80 MB/s per device. This is, however, a lower rate than parallel NOR can achieve.
High-end systems that must provide both enhanced GUI and instant-on features will thus likely need a hybrid architecture solution in order to achieve their highest potential and optimal performance. One such architecture uses the HyperBus memory interface, developed to satisfy the need for higher read/write performance, while remaining sensitive to the pin count constraints of modern MCUs. It exceeds the speed of parallel NOR flash and adds only a handful of pins to Quad SPI flash, giving it the ability to satisfy the memory requirements for both volatile and non-volatile memories for a large variety of high-performance applications.
This architecture is already being fielded. One example of the HyperBus interface in action is its use with Cypress’ 2D and 3D graphics-enabled Traveo automotive MCU family, which is based on the ARM Cortex R5 core. HyperBus memories, including Spansion HyperFlash and HyperRAM memory, are being used to provide customers design simplification and faster performance in automotive dashboards. Freescale is also using the HyperBus interface in its MAC57D5xx Automotive DIS MCU as well as a number of other platforms.
The Future of the “Instant On” Experience
Whether or not you agree with Harry Gordon Selfridge’s popular phrase “The customer is always right,” I can guarantee you that someone else does. In today’s world of ‘right now' and ‘on demand,' we can expect the instant-on trend to continue for the foreseeable future. We can also expect throughput to surpass current speeds and densities to continue to grow, and hybrid approaches like the HyperBus interface to expand into other types of memories, beyond flash and RAM. With compelling benefits such as low latency, high read throughput and low pin-count, more chipset companies will adopt the hybrid standard and more embedded designers will develop the next generation automotive applications and other electronics on these hybrid offerings.
—Hiro Ino is senior director of the NOR flash products business at Cypress Semiconductor.