Almost at the same time that Micron was withdrawing the last of its phase change memory (PCM) products from their standard products list (in December 2013) they were issued with a new PCM related patent, US No. 8605490 B2, which breaks some interesting new ground. It combines the speed advantages of the performance of an SRAM with the non-volatility of a PCM, the holy grail of a unified memory. It is noteworthy that the inventor cited on the new patent is Richard Fackenthal, who was also the lead author on the recent Micron-Sony 16Gb ReRAM paper at ISSCC 2014. This may be interpreted by some as confirmation of a new direction of emphasis from PCM to ReRAM for Micron.
While the patent examiner's references cited more recent activity, the operation of device on which the new patent is based has a history and prior art that can be traced back to an invention by IBM called latent image memory. The details of this were published as far back as 1970/1971.
The principles of the latent image device are relatively easy to understand. If you construct a perfect cross-coupled SRAM (perfect as is in every aspect of its structure, width, thickness, and resistance of conductors, gain, or capacitance of the transistors, etc.) and then gradually apply the power by increasing the applied voltage, then the data contents of the memory will come up in what appears to be a completely random state, as might be expected. However, with power applied slowly, that same memory array will always come into full operation with the same initial data content, a latent image. In fact, the data content of the memory will be determined by the smallest of differences in the resistance of the conductors in the two sides of the bi-stable element that makes up the cross-coupled SRAM bit. Once the memory array is fully powered then it can be operated in a normal manner as a high speed SRAM, the small biasing differences will be ignored.
In order to avoid the normal as fabricated randomness of the latent data, the IBM developers deliberately made one of the conductors in one of the branches of the SRAM circuit slightly narrower or modified other components in one branch of the circuit. This predetermined the latent image and, in doing so, realized the possibility of creating a non-volatile memory (in effect a read-only memory, ROM), hidden or latent beneath a normally operating SRAM without compromising the normal operation of the SRAM. They called this a latent image memory (LIM).
I believe that while the Micron work is commendable (including the free-running bistable oscillator where the resistance of the PCM controls the frequency), an opportunity to create a memory that is able to learn has been missed. (This is discussed in more detail in the later paragraphs of this article.) In IBM's original work on their latent image memory, the narrowing of a conductor was all that was necessary by way of a resistance change to provide the bias that would determine the latent state of the memory. For me, that fact raises the intriguing possibility that it should be possible to use the principles of the latent image memory to create a memory that can learn. Such a memory would not require the phase-change material, or other materials for that matter, to be switched, but would employ changes that accumulate with time and exposure to changes in its local environment, e.g. thermal, electrical, or both.
The Micron version of the SRAM-PCM hybrid uses the latent image effect by putting a PCM cell in each side of the cross-coupled SRAM cell as shown in Figure 1. Each hybrid SRAM cell has two distinctly separate circuit blocks, encircled in blue or brown in Figure 1, each with its own read/write programming input.
In the patent, the Micron inventor describes the operation of the memory cell as requiring one of the PCM devices to be in the set (low resistance) state and the other in the reset (high resistance) state. This provides the necessary high or low resistance difference between the two branches of the SRAM circuit that is required to ensure the cell will remember the latent image data that was loaded into it. To use the background data, the cell and the array will still require the time latency inherent in a latent image memory to ramp the power up. The latent or background data programmed into the PCM and the value of the resistance of each of the two PCM devices must be chosen so that it does not impede the normal SRAM operation of the memory.
Latent images and learning
It occurred to me that it might be possible to use the latent image effect to create a form of SRAM memory that has the capability to learn without the added circuit complexity required for programming the PCM cells. More recently, IBM spent a lot of effort and ingenuity to deal with the problem of drift that occurs in the high resistance state of PCM memory cells. This is an especially troubling problem when attempts are made to use PCM in a multi-level mode. This drift in resistance occurs naturally, and its rate varies as a function of the local thermal environment.
It might be possible to use this effect, or a similar effect in other materials, to create a memory array that remembers its most often used data state in the form of a latent image. The way this might be achieved for PCM material is to construct a hybrid resistor that consists of a normal resistance material in parallel with a resistor film of chalcogenide material. The implementation would require intimate contact between the two resistors. Then, any current passing through the resistance combination would by thermal coupling cause the rate of drift towards higher values of resistance to change and, because drift is essentially an annealing process, increase the rate, causing a change in the total value of the two resistors in parallel to move to a higher value.
Shown on the right hand side of Figure 2 is an example of a simple version of the of the proposed Learning Latent image-SRAM (LLi-SRAM) circuit, the hybrid resistors are shown in each branch of the cross-coupled SRAM cell circuit. The resistors consist of a film of chalcogenide in a suitable resistance state, achieved during processing, overlaid on another resistance material.
On the left hand side of Figure 2 is an imagined sequence of operation with the learning process taking place. Initially both resistors, the red and blue lines, drift together. Then, power is applied and the SRAM is operated in the normal manner. However, the highest rate of drift will be determined by the side of the SRAM that spends most of the time in its conducting state. At the end of the period, off operation power is removed and the chalcogenide material of both resistors drifts in the normal manner. When the power is ramped up, the data contents of the memory are determined by the latent image determined by the difference in resistance value between the two resistors.
The next step in time (see Figure 2) is what happens when a change in temperature to a higher value occurs. This will mean that the effects of annealing and the temperature coefficient of resistance will compete, the high value of the temperature coefficient of resistance of the chalcogenide material will dominate, and the resistance of each resistor will decrease. Then again without power the drift will continue at a constant rate for both resistors.
The next step in Figure 2 shows what happens after the power is again ramped up, and the memory is operated with the other arm of the SRAM mostly in its conducting state. The two resistors both change values. But when power is removed, the latent image of the memory cell has changed and will be observed on the next power ramp up. Following that is a sequence with power down and another temperature change back to the original starting temperature.
If, with temperature and time the resistance of the amorphous material starts to reduce due to crystallization, then a similar argument can be made for the operation of the LLi-SRAM. If the crystallization is due to the effect of elevated temperature of the environment in which the complete array exists, then the rate of change for the two hybrid resistors will be the same. If the crystallization is from thermal or other effects of current flowing through the resistors, then the rate of change will be different and the LLi-SRAM cell will operate in the same manner and create a latent image, as it did for drift.
The LLi-SRAM idea is possibly a flight of fancy. However, as suggested earlier, it might be possible to move away from chalcogenides to other materials where interacting surface effect between any two resistance materials in contact can result in larger resistance changes when current flows through the combination. It might be possible to find suitable materials or other NV memory types that use switching mechanisms different from PCM, where the resistance changes occur as a result of current flow. The Micron patent uses two variable resistance PCM devices to establish the latent image, which means that a single set or reset pulse applied to each device will ensure a resistance difference sufficient between the two to ensure the intended latent image is written. It would also appear that if an iterative write/erase was to be employed, the SRAM could be designed with just one PCM.
The earlier latent image work at IBM demonstrated that only the very smallest of differences in resistance between the two arms of a SRAM cell that occur in even the best fabrication process are all that is necessary to determine the logic state of the latent image. With relatively small differences, as would be the case with the LLi-SRAM design described earlier, some serious simulation work should quickly determine the minimum resistance changes that are acceptable to achieve latent image operation.
- Latent Image Memory, I.T. Ho and G.A. Maley, IBM Components Div., Hopewell Junction, N.Y., R. Waxman IBM Systems Development Div., Poughkeepsie, N.Y., Proc. ISSCC 1971, pp. 82, 83