You've probably heard the saying "It's what's inside that counts" or some version of it. Typically this is meant to indicate that a person's personality is more important than physical appearance. Though I recently enjoyed a television commercial for a newer M&M candy version with a pretzel inside and the animated chocolate candy character says, "You're going to put what, where?" with a concerned look on his face. But I digress. When it comes to automatic test pattern generation (ATPG) for digital ICs, cell-aware testing looks more at the inside of a circuit than traditional ATPG models.
If you're not familiar with fault models, they are basically meant to mimic actual defects that can occur in the manufacturing process of ICs. Traditional ATPG fault models include stuck-at, transition delay, path delay, bridging, and other conditions. ATPG software creates test patterns that obtain high test coverage of the specified fault locations for the desired fault model. All of these models place the fault target locations on the pins external to the cells used in the design, so what gets tested is the interconnect between cells and most -- but not all -- of the internal cell defects.
The traditional ATPG fault models find most defects, and that's good enough for many ICs. But there is an increasing number of ICs, for medical and automotive applications in particular, that are held to higher standards.
This is where cell-aware ATPG comes in. It is a newer ATPG-based test methodology that achieves higher test quality because it's doing something that traditional ATPG does not. Cell-aware test is looking inside library cells used in the IC design by targeting specific defects such as opens and shorts of transistors inside those cells. A cell could range from a basic logic gate to something involving many gates.
As transistor and interconnect sizes continue to shrink, the degree of difficulty to manufacture them without any defects rises significantly. In addition to the reduction of component sizes, many cells are also becoming more complex. As a result, 50% of defects now occur within the cells. It's more important than ever to test for defects within the cells.
Like all great things, cell-aware test comes with costs. The first is the one-time setup cost of doing a cell library characterization to determine where defects can occur inside each cell and how the defect would affect its operation. This characterization creates a user-defined fault model (UDFM) file to use with the ATPG tool that describes all the cell inputs and responses needed to detect the characterized defects. The UDFM file creation step is done just once for any particular technology design library. Then that same UDFM file can be used for the ATPG of all other designs using the same technology library.
A second cost of adding cell-aware test is that it creates more test patterns, which require more tester memory and test time. Of course, most designs also include the use of on-chip test compression logic to reduce the impact of test pattern volume, so this cost can be held to a reasonable amount.
The cell-aware model generation flow is illustrated in Figure 1. The process starts with the extraction on the physical cell layout library, which provides parasitic capacitances and resistances to locate potential defect sites for bridges and opens. Then you define the types of defects you want to model and perform analog fault simulation. This results in a defect matrix that is used to generate the actual cell-aware UDFM model to use with ATPG. The ATPG flow is the same as for other fault models except for the inclusion of the UDFM file.
After a onetime library characterization, the cell-aware flow is the same as any ATPG flow. Click here to enlarge.
Several published case studies with real silicon results show how some ICs that pass the standard set of stuck-at and transition-delay test patterns will fail the cell-aware tests. One was on an AMD 32nm processor, the other a Freescale 55mn automotive microcontroller.
Catching these defects early in the manufacturing cycle is critical for two main reasons. First, it costs much more when these defects escape ATPG test and are found later in system test or when they get into the end product or the customer's hands. Second, if the defects can be caught early and diagnosed, then fixes and improvements can be implemented in the manufacturing process to increase yield and profitability.
Please share your ideas or experiences with cell-aware test.