Unclear how to interpret the stability
Engineers may not recognize control loop stability issues from closed loop performance (or the ramifications). For example, the impedance plot below shows the output impedance of an LM4050 voltage reference with a 1uF capacitor. (No additional details about the cap are provided.) This device also shows a typical phase margin of approximately 12 degrees. The inexperienced or untrained engineer will not recognize the looming stability issue, the ramifications for circuit performance (including degraded PSRR, crosstalk, noise, reverse transfer, and voltage excursion), or the possible consequences for downstream circuits that connect to this device -- an ADC, for example.
Another datasheet example clearly showing poor stability,
though it may not be easy to interpret.
This assessment is supported by the fact that I find so many circuits with control loop stability issues.
Different operating conditions than the datasheet
The datasheet example also shows that different reference voltages produce different stability results. This is also true of different reference bias currents (or output currents in the case of the linear regulator) and different capacitor values. The graph is for a bias current of 100uA. The published data is often not shown for the operating conditions applied in the circuit being assessed.
Contradictory or dated information
Many device datasheets tell us to use tantalum capacitors on the outputs of our linear regulators. One issue is that the ESR of these capacitors has been continually dropping as technology has advanced. Unfortunately, this degrades the control loop stability.
There is also frequently contradictory or conflicting information reaching the design engineers. The linear regulator might state that moderate ESR capacitors are recommended, but then the datasheets for the digital circuits and op-amp connected to the device (often from the same manufacturer) recommend ceramic capacitor decoupling for every chip. As circuits become more complex and use less power, we are connecting ceramic decoupling capacitors, negating the benefit of the moderate ESR recommendation. It is not unusual for me to see more than 50 ceramic capacitors connected to a single voltage regulator.
High-speed op-amps and multilayer circuits don't always get along well together. The high-speed or high-bandwidth op-amp -- especially when used in a unity-gain or low-gain configuration -- is sensitive to much lower values of capacitance than either a voltage reference or a linear regulator. There are two sensitive nodes: the op-amp output and the op-amp inverting input. Large pads on multiple-layer PCBs can result in significant capacitance, especially when using wider traces and larger device solder pads, as well as signal and grounds on adjacent layers.
Solving the issue
First, it is important to get data at the operating bias conditions of the intended circuit. The simplest data to obtain is the output impedance measurement. There are many application notes on the Picotest website about making this measurement and assessing non-invasive stability.
With the impedance information in hand, we might now recognize that the device impedance appears as a series resistor and inductor (as identified by the +6dB/octave slope of the impedance curve). Converting this impedance measurement to an inductance,
For example, the plot at the top of this page shows that the 2.5V reference configuration has an impedance of approximately two Ohms at 1kHz or 318uH.
The inductance can also be calculated from the resonant frequency and output capacitance, as in
In this case, the plot shows that the 2.5V reference configuration has a resonant frequency of about 1kHz with a 1uF capacitor.
With both the inductance and capacitance defined, the value of the desired ESR can be estimated by setting the resonant Q to 0.5.
This ESR value is not realistic, but it is possible to add 36 Ohms in series with the capacitor to produce stable performance. The resistor can also be placed between the active device and the capacitor or (optimally) equally split between the two locations, with half the resistance connected to the active device and the other half connected in series with the capacitor. Of course, the non-invasive measurement is simple and inexpensive and provides the data required to achieve an ideal solution or to assess the stability in circuit quickly.
Have you seen evidence of stability issues in your circuits? It could be the reason for unexpectedly high clock jitter, circuit noise, or excessive EMI. Do you think device manufacturers could do a better job of providing stability relationships for their devices?