Steve Sandler finds that eight out of 10 design issues are due to a single problem that is easy to solve.

The vast majority of design issues are directly or indirectly attributable to control loop stability. The most common offenders:

Linear regulators

Voltage references

Op-amps

The control loop stability of these devices can propagate through an entire system. Symptoms include:

EMI

Increased circuit noise

Clock jitter

These are all simple circuits, so why is this a common issue?

We are not clear on the definition of stability
In the high-reliability world, including satellite systems, where I do most of my troubleshooting, stability means a minimum phase margin of 30 degrees and a gain margin of 6dB at the end of life, including all component variations and environmental factors. There are guidelines that define the stability margin limits, and one of our tasks is to ensure that margin.

This requirement is not well aligned with the information given out by manufacturers. They generally do not provide quantifiable metrics for the stability of their devices. In many cases, the devices will not meet a 30-degree phase margin even typically when coupled with low-ESR capacitors. The definition of stability in the semiconductor world seems to be whether the circuit has a stability margin that is greater than zero.

Component manufacturers drive us to it through recommendations
In some cases, manufacturers provide recommendations. One example I often use is the REF02 voltage reference. The manufacturer's datasheet highly recommends the addition of a 0.1uF output capacitor on the voltage reference.

An excerpt from the REF01/REF02/REF03 Rev K datasheet.

The highly recommended output capacitor is shown in two different schematics in the datasheet.

One of the two schematics in the datasheet showing the recommended 0.1uF output capacitor.

Inability to measure directly
The results of following this recommendation can be seen in the ringing produced by a small signal step load.

Step load of the reference from 167uA to 437uA. The yellow trace shows the reference output voltage with the highly recommended output capacitor. The white trace shows the voltage without the recommended capacitor. The blue trace is the load current.

The results also show up in a VNA measurement of the reference output impedance.

Output impedance of the REF02 without (dashed line) and with (solid line) the recommended 0.1uF output capacitor.

One reason engineers get into so much trouble with the control loop stability of these types of devices is that, in many cases, the access to the control loop is not available, so it isn't possible to measure stability directly using traditional Bode plot techniques.

Even though measuring the phase margin directly is not possible, a non-invasive stability method shows the phase margin of the recommended circuit to be about 12 degrees in the typical case.

You are mostly, but not entirely correct. The stability definition you presented is reasonable, the question is the metric for quantifying the margin of stability, which in most cases is the closest proximity of the gain vector to the singular unstable point (1,0).

The ringing is not quite preditcable, as it has much to do with the degree and Q of the open loop, which is often unknown. The issue is particularly troublesome in circuits where the loop is not accessible for measurement. This is often the case with class D monolithic audio amps, voltage references and fixed voltage regulators to name a few. So for example if you look at a LDO datasheet and it says stable for capacitors from 1uF to 100uF what exactly does this mean? Will the circuit ring? If so, how much and do we care?

I'm currently writing a new book for McGraw-Hill on high fidelity measurement and it will address some of these issues and how they propagate through systems. The book should be submitted to the publisher in early 2014.

The point of this article is that we should be concerned about even a little bit of ringing (especially in a high performance system) might rwreak havoc on the performance.

G'day all, I am a professional engineering undergraduate student in the degrees of Computer Systems Engineering and Computer Science at Curtin University of Western Australia.

I was taught (and I have read in many books on control system theory), that the definition of a fully-stable system is one in which one or more bounded inputs to the control system (i.e. The transfer function), results in one or more bounded outputs (for SISO and MIMO systems). Put another way if a finite input results in a finite output; put yet another way (in terms of the impulse response of said system), if the impulse response of the system tends to zero after "some" time.

You can have marginally stable systems where the impulse response tends to some finite non-zero value but never goes to zero. Hence a system is unstable (in terms of the impulse response), if the impulse response reaches infinity after a certain time. [Ref: "Electronic Devices and Amplifier Circuits with MATLAB computing", Second Edition by Steven T. Karris, Orchad Publications 2008 [ISBN-13: 978-1-934404-14-0, ISB-10: 1-934494-14-4].

Sidenote: The impulse response in the digital domain is simply a vector (of necessary length (n)), that contains a 1 followed by n-1 zeros.

With respect to the ringing due to the output capacitor, this is entirely predictable I thought. Without the capacitor (in combination with the output impedance), you have all frequencies passing through (due to the input of Dirac-delta function equivalents at the start and end of the square wave pulse), resulting in an approximation of a theoretical impulse (we are in the analog (or analogue) world now :)). With the capacitor much of the high-frequency components have been filtered (passed-through to ground) but some low-pass signals have passed through. In any case the system (or more commonly subsystem) still appears fully-stable in theory as the output voltage is tending to zero; the problem comes when this is inputted into the next stage. This is all undergraduate stuff so I must be missing something!?!?

With regards to not being able to measure something in one's design; if you can't measure it you can't test it and if you can't test it then you may be in trouble. One would have to go back and think how do I know the existence of something that can't be measured? In general it is because some [acceptable number of] mathematician/physicist says it has to be there in theory. One may have to look at what the unmeasurable object affects, with a view to being able to measure the effects and work backwards with theory (math).

great points, thanks for sharing. Yes, we also often use high performance shunt regulators in sensitive applications, both because of the reasons you mentioned and also the superior noise and PSRR performance, but they are not efficient and so most designers avoid them without due consideration.

The proliferation of local bypassing is indeed a problem. I work with layout people who lay down 100nF caps for every package whether I specify them or not. Sometimes they are needed, often not. When I have done other designs I will decouple with something like a 10 ohm resistor in series, which may still be too low depending on the regulator. This of course complicates matters as well if some stiff regulation at a particular load point is assumed and required. Also, the approximation to zero potential of a ground plane is just that, and mingling signal commons with power commons in the presence of rapidly fluctuating loads inducing currents through all of those bypass caps can spell disaster.

Sometimes the bast way to proceed is local fast shunt regulation, although it entails substantially higher quiescent current. But it can render local current fluctuations small enough to allow grounds to be shared, which is helpful at very high frequencies.

Certainly, and thanks for asking. Since the voltage regulation loop appears as an indcutor there regulator with a capacitor forms an LC network. The ESR provides the majority of the damping. The charaxteristic impedance, Zo, of the LC circuit is SQRT(L/C) and the Q is defined as Zo/R. If R is mostly ESR and we set the Q to 0.5 for optimal damping you end up with the formula indicated.

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