In the first column in this mini-series, I looked at the SmartFusion2 FPGAs from Microsemi. Now I will give my take on the IGLOO2 family.
Microsemi has recently released IGLOO2 to address new designs. This is the second new FPGA family since Microsemi acquired Actel. In today's column I will look at the IGLOO2 product features and compare them to competitive offerings. In my next column I will investigate some of the more esoteric aspects of Microsemi's devices.
The IGLOO2 family covers the same density range as SmartFusion2 and tops out at 150 k logic elements. Compared to the original IGLOO range, this is around an increase of six times in maximum density, and places the IGLOO2 firmly in the medium performance, low-cost sector of FPGA offerings. The family starts with a tiny 6 k logic element device, while the bulk of the complexity range is already covered by numerous devices from other vendors, such as the Arria II, Cyclone IV, and V devices from Altera; products such as XP2, ECP3, and iCE40 from Lattice Semniconductor; and components like the Spartan-6 and Artix families from Xilinx. Customers have plenty of choice and data sheets to scrutinize and compare.
In a recent webinar, Microsemi compared IGLOO2 against the Cyclone V and Artix product range. The new family has a strong focus on security, including dedicated encryption and physically unclonable function (PUF) blocks, which -- together with user Flash memory blocks and the low standby current -- are clearly not supported in the families chosen for comparison. Other features such as DSP blocks, PCI circuits, and memory controllers are commonly found in competitor products. Microsemi chose to highlight the number (up to 16) of 5 Gbit/s transceivers, even though the largest Artix is slated to have 16 instances of 6.6 Gbit/s and the Arria V range features 24 SerDes transceivers at a similar logic complexity. The company claims that IGLOO2 features the industry's only high-performance memory subsystem, with DDR2 clocking at 333 MHz. Both the Artix and Cyclone data sheets indicate a faster data transfer capability. However, neither includes non-volatile memory. Historically, Microsemi (formerly Actel) devices were not thought of as having a fast programmable fabric compared with the competition, and that begs the question how comfortably the new chips can process ingress and egress data totalling 80 Gbit/s. I would certainly expect that the fabric on the 28 nm SRAM parts that Microsemi chose as a comparison would be faster than the 65 nm flash-based IGLOO2 devices.
Excerpt from the FPGA and CPLD comparison chart from High Tech Marketing showing IGLOO2 compared to competitors for the smaller devices.
(Click here to see a larger, more detailed image.)
One advantage for IGLOO2 is that these devices can operate with only two voltage rails, although it has three supplies that may all need different voltages depending on the system requirements.
Another differentiation claimed by Microsemi is the high level of I/O in the devices. It is correct that, compared to Cyclone V and Artix, the IGLOO2 have more pins. However, if it's pins that you need, then an alternative for the smallest device in the IGLOO2 range might be found in the Lattice iCE40, XP2, or MachXO2 ranges which have similar numbers, while larger parts are matched by the Xilinx Spartan-6 or the Cyclone VI family from Altera.
IGLOO2 devices do consume low quiescent power, which is quoted as 10 mA. This is lower than SRAM-based FPGAs that suffer additional leakage from the transistors used to store the device configuration. IGLOO2 devices also look good compared with the Lattice XP2 family, which is also built using flash rather than SRAM programming elements. Additionally, there is a standby mode which can be used to freeze the
IGLOO2 devices while the system is idle. For ultra-low power applications, it will come up against the non-volatile Lattice iCE40LP LP8K, with its very frugal supply current of 360 µA.
Included in the High Performance Memory Subsystem (HPMS) on the IGLOO2 family are up to 512 kBytes of flash memory, which allows users to store system data such as Ethernet MAC IDs, user keys, system configuration, and system personalization data. This embedded Non-volatile Memory (eNVM) feature also enables secure boot functions for external processors by storing secondary boot loaders securely on-chip. As with the SmartFusion2 products, my advice is to consult the data sheet to familiarize yourself with the endurance limit for the number of read/write cycles. For the eNVM, this is between 1 k and 10 k cycles, while the limit for reconfiguring the FPGA fabric itself is 500 cycles.
Unlike the SmartFusion2 products, what IGLOO2 does not have is any hard or soft processor solution. Xilinx and Altera support soft processors across their range, as well as hard ARM cores in the Zynq and Cyclone SE, ST, and SX parts. Although Microsemi does not position IGLOO2 as "SmartFusion2 without ARM processors," this is one way to consider the family.
The design tools are built on the Libero suite, featuring synthesis, debug, and DSP support from Synopsys and simulation from Mentor Graphics, augmented with power and timing analysis. Soft cores are used to build functions such as coding, which are not supported as hard implementations in the silicon. The web currently lists over 30 cores targeted at IGLOO2, against a richer offering for the competitors.
What about pricing data? Microsemi included the following note in their press release: "Pricing for IGLOO2 starts at less than $7USD for high volume orders." This will presumably be for the smallest device (M2GL005) with just 6 k logic elements in a VF400 package for volumes of, say, 250 k units. In terms of density, this pitches it against the Xilinx Spartan-6 (XC6SLX9) or Altera Cyclone IV (EP4CE6), both of which I would expect to be competitive on price.
In summary, the mix of capabilities and features in the IGLOO2 will be attractive in a number of applications. Microsemi has a focus on applications requiring security and reliability, and these are aspects that I will discuss in my next blog.