Although the semiconductor industry has benefited tremendously from 50 years of Moore's Law there is also broad recognition that the era of regular process shrinks may be, for many, approaching an end.
A complex mix of technologies and design methods collectively referred to as "More Than Moore" is replacing that regular miniaturization. One of the most promising technologies is the vertical stacking of dies using through-silicon-vias (TSVs) for die interconnect to create a 3D circuit.
The promise of 3D includes greater functional density, reduced footprints, and lower power consumption, because the distance and capacitance of interconnect can be reduced. However, as the technology matures, as business models evolve, and as 3D design standards emerge, another issue hangs like a cloud over the landscape. That cloud, which could prevent, or at least delay, the broad market adoption of 3D circuitry is patents.
A casual Internet search for "design of 3D circuits patents" quickly reveals at least five patents describing methods and systems for the design of 3D ICs, focused on design software tools. Finding further details is left as an exercise for the reader.
These sets of patent claims address data structures for 3D design software. The claims appear to be fundamental enough that it could be impossible to work around them in any design tool implementation, assuming the claims stand. Furthermore, licensing is exclusively controlled by a non-practicing legal entity that is currently suing both EDA and end-user companies, with no indications of any quick settlement on the horizon. This legal climate, now preventing or delaying 3D-capable EDA tools, will necessarily have a similar impact on a pipeline of 3D designs, constraining the market for 3D manufacturing and commercialization.
Several years ago, Si2 formed the Open3D Technical Advisory Board (TAB), which comprises 17 corporate members. Its charter is to develop or extend standards to support 3D design flows. The group has been quite productive: a power distribution network standard -- defining interfaces between multiple dies and the package -- was released in May; a new 3D thermal constraints standard is imminent; and four additional standards are in development. Fortunately, exercising Si2's IP policy brought the 3D patents to light earlier in the year, when it was determined that none of the Open3D standards was impacted. Yet the lingering IP issues to be addressed when actually implementing 3D design-tool flows remain serious concerns.
A range of approaches to resolve the situation are currently under active discussion in the industry and at Si2. Please contact Si2 for additional details on this topic and how you can help industry advance the More-than-Moore approach to circuit integration while respecting appropriate and valid IP rights.