I just heard from my friend Dr. FPGA (a.k.a. Dr. DSP, a.k.a. Warren Miller) that he will be giving a free one-week online course on SoC-level FPGAs starting today, Monday, Sept. 23. Click here to register.
The course will last one hour a day starting at 2:00 p.m. ET/11:00 a.m. PT/7:00 p.m. GMT/UMC. Don't worry if you can't make it each day. You can always view the archived version of each lesson. Having said that, it's always better if you can tune in to the live presentation, because you can take part in the question-and-answer session at the end.
A traditional system on chip (SoC) is a custom-built device that uses ASIC technology and includes one or more on-chip processors (MPUs, MCUs, DSPs, etc.); some on-chip memory; and on-chip peripheral, communications, and interface functions. The more recently developed SoC FPGAs combine traditional SoC functionality with programmable FPGA fabric.
In some cases, the processor may be a single-core ARM Cortex-M3. In other cases, the SoC FPGA may boast a dual ARM-Cortex-A9 with on-chip caches and floating-point units. In addition to substantial amounts of on-chip memory and high-speed external memory interfaces, the SoC FPGA may include a variety of external interface functions -- SPI, I2C, CAN, UART, and so forth. All this is augmented by programmable digital fabric that interfaces with the processor cores via high-speed internal busses. Some SoC FPGAs also boast programmable analog functionality.
In addition to the various SoC FPGA devices and tools that are available, Miller will discuss the key elements you need to consider when using these rascals in your designs.
I'm looking forward to this. I always enjoy hearing Miller speak. Hopefully, I'll see you there.