There are a number of considerations for design and development teams when dealing with high-speed test. As semiconductor geometries shrink, it has become possible to push the boundaries of high-speed serial interfaces up to and beyond 28 Gbit/s while adding additional features. This presents many challenges to the test development industry. There will often be tradeoffs among the chip functionality, IP licensing fees, real-estate used, and added costs to implement features. This has to be balanced against the increase in ongoing production costs if certain features are not implemented.
This will be the first in a series of blogs dedicated to identifying and addressing the challenges faced by the design and development team. This particular article will focus on high-speed test capabilities.
1. The development team must decide what features they will incorporate into their chip design to enable self-test within the ICs, including:
- PRBS generators
- Error counters and PRBS checkers
- Analog control on transmitters to open and close eye height
- Jitter injection on transmitters to further close the eye to stress receivers
- Analog receiver circuitry to adjust the capture window
- Calibration circuitry to optimize receiver/transmitter performance
2. The designers must work with the design for test (DFT) and test development team to assure they have included the necessary hooks, tools, and documentation to enable the test team to access the built-in features. This usually includes a lower-speed access bus to control internal registers; normally an SPI, MDIO, or JTAG type interface is used. This bus is of little use unless there is also a mapping of the registers to the internal chip functions, and a timing diagram to assure proper programming.
3. Features that are not built into the chip design will have to be identified so alternative coverage techniques can be implemented. Many tradeoffs will have to be made here depending on the time-to-market and type of market targeted. These include answering the following questions:
- What equipment do we need to verify/characterize, and what is cost and availability?
- How is calibration to be performed if required? (Note: Most chips in the 28 Gbit/s range and above require some calibration/trimming.)
- What percentage of coverage is lost?
- Is there another way to test externally and keep the cost down? For example, can we test the existence of the physical connection and basic DC characteristics and correlate to performance or trim values?
- Will this lack of features effect QUAL testing and coverage?
4. Additional questions will need to be answered to prepare for qualification testing, including the following:
- Can any of the high-speed interfaces actually be tested during stresses like HTOL, or will they simply be turned on or off and left running in a terminated structure?
- Will the chip be able to be placed into lower power mode for package-level qualification?
- Will the high-speed interfaces be exposed to ESD stresses?
- Have the ESD structures been incorporated on all pins or just the lower-speed interfaces?
- Does the design require high-speed clocks (often > 700 Mhz) to operate in any of these modes? If so, will these clocks handle the high stresses the part is exposed to?
5. For equipment decisions used during characterization and production testing, the following questions also need to be answered:
- Will the testing be done all at system levels for production?
- Is the product used internally or in a customer’s end product?
- Will there be bench equipment?
- What are the capital costs?
- Can characterization and production testing be done on the same systems?
If the decision is made to use the large ATE systems, what are their capabilities and restrictions?
- Does it have any high-speed capability?
- Can the device work at a lower frequency?
- Is the system available in subcons?
- What are the costs of test using different models and systems
- Will the production testing be done with loopback?
- What is the system DC and AC accuracy for trimming and calibration?
- If the testing uses loopback, are the high-speed channels connected to tester channels for DC measurements necessary? This will involve either bias tees or a switching architecture.
While this is not a complete list, there is a significant amount of upfront work that goes into the decision-tree for high-speed testing, and it can get very involved and lengthy. It is important to find partners that understand and can assist in many of these decisions to alleviate or minimize many of the barriers to entry into the market of high-speed devices. By teaming with the right partners, you can mitigate many of the risks that can stop or significantly delay the successful release of your product to market.
Next time, I will discuss hardware design for testing high-speed serial interfaces on ATE systems.
— Lance Jones is VP of Technology, Microelectronics Test, and Engineering (MTE) at Evans Analytical Group.