The recent port of a number of mixed signal interface IP blocks to 20nm by Synopsys raises some fascinating questions on the microprocessor ecosystem.
The recent port of a number of mixed signal interface IP blocks to 20nm by Synopsys Inc raises some fascinating questions on the microprocessor ecosystem. In days gone by, analog was well behind the curve. Now, USB, DDR, PCI Express, and MIPI PHY interfaces are available at what is pretty much the leading edge.
The Synopsys' EM family provides highly configurable cores where instructions can be added to accelerate specific applications -- ideal as the controller for memory or an interface that doesn't have to worry about running an operating system. This makes them well suited to the interfaces that have been ported to TSMC's 20SoC process.
On the 20SoC process, the EM4 controller should be able to top 1GHz and run as low as 2.8mW. In the process it could take up around 0.005 sq mm, which is mind-bendingly small but again plays very well to the interface controller. Yes, those are the right number of zeros -- the core is 0.1mm on a side in 28nm.
The IP ecosystem for SoC has become vitally important and the current battle ground for several suppliers, and the interface is an important one for Synopsys. While the world is focused on ARM and its ecosystem of physical IP and software support, Synopsys also has been working away with its configurable processor acquired from ARC International Ltd via Virage Logic Inc. Cadence Design Systems has been taking a similar approach with its acquisition of Denali for its memory compilers and Tensilica for customized audio and DSP subsystems.
While it comes as an RTL output from the configuration tools, there's a big step from RTL to the double patterned 20SoC process and an even bigger step to 16nm FinFET. But the area figure for the EM core shows how much tolerance there is to play with as part of the integration.
"By offering a broad portfolio of IP for the 20nm process, Synopsys enables designers to more easily meet their goals of creating differentiated products with less risk and faster time to volume production, while also reducing the risks associated with moving to the 16nm FinFET process," said John Koeter, vice president of marketing for IP and systems at Synopsys.
It is interesting that Synopsys sees this as a step to FinFETs at 16nm. The double patterning techniques at 20nm come with some challenges, as this uses two photo masks, each with half of a pattern, to enable printing of images below the node's minimum spacing design rules
These ports are not trivial, and these blocks are also traditionally areas where it is difficult to add additional value, so they are essentially an overhead. Getting a high yield with the more complex double patterned 20nm process for these mixed signal blocks is a key step, both for Synopsys and for the SoC designer. The processor is sure to follow to allow more value to be added in software, enhance the performance and add new features as part of a platform.
The EM cores were developed in the UK with ARC, which was bought out by Virage in 2009 and then Virage was bought by Synopsys in 2010. This leaves Synopsys with a team of processor designers in the UK with specialist knowledge of configurable architectures.
Synopsys says it has 80 test chips in 20nm and 28nm. I'm willing to bet the majority of them are in 28nm, although the eye diagrams for the 20SoC PHY blocks look good. With those available, the focus moves to the controllers such as the EM.
The importance of this is highlighted by Synopsys planning to launch a new family of EM controllers in the next few weeks. The new architectures will have to cope with GHz speeds for a trickle of power in 0.1 sq mm, which is 20 times the area to play with. But the most important part is having the ecosystem of interface IP available. Then the story becomes very interesting.