SERDES links screaming along at 28 Gbit/s are not trivial to validate and measure. The design and de-embedding of the test fixture path, along with the instrument set-up, play an important part in the process.
SERDES links screaming along at 28 Gbit/s are not trivial to validate and measure. The entire serial transmission and measurement ecosystem must be considered to characterize the waveform and jitter performance at the device pin accurately. Even the best of characterization boards will end up with signal-degrading vias, transmission lines, and connectors on the path from the device to the measuring instrument. Accurate de-embedding requires careful selection and measurement of calibration structures.
Measurement-based model building enables verification and optimization of the measurement reference planes. Additionally, the PLL, bandwidth, and peaking enable the recovery of accurate and compliant jitter measurements with sub-picosecond resolution. The design and de-embedding of the test fixture path, along with the instrument set-up, play an important part in the ability of an oscilloscope to recover the undistorted waveform from a transmitter pumping out bits every 36 pS.
The above two paragraphs are the abstract for a white paper on characterizing a 28 Gbit/s transceiver. The 31-page paper is written by five engineers: Jack Carrel, Xilinx; Robert Sleigh, Agilent Technologies; Heidi Barnes, Agilent Technologies; Hoss Hakimi, Xilinx; and Mike Resso, Agilent Technologies.
The paper includes the following topics:
Overview of a 28 Gbit/s SERDES channel (including PCB layout and signal chain diagram)
- Test fixture calibration structures (including calibration test fixture design)
- Test methodology
- Test fixture characterization (including very detailed discussion of fixture de-embedding and oscilloscope measurement techniques)
- 28 Gbit/s SERDES measurements (step by step guide).
The text of this paper is available as a free download here.