Etienne Racine, technical marketing engineer in the Silicon Test Solutions products group at Mentor Graphics, shares thoughts on how to apply BIST to external DRAMs in this design article on EDN.
Here’s a quote from the article’s introduction:
3D-stacked designs containing a mix of separate logic and memory die represent a somewhat new application for memory BIST (built-in self-test), compared to the more conventional, single-die embedded SRAM implementations. Gaining access to a DRAM requires predefined customized memory operations. EDA tools must make this definition step as simple as possible, while ensuring it can be reused across designs and over time. We also see that traditional test algorithms are less efficient on DRAMs, so they must be reconsidered in a 3D-IC context.
The author concludes that memory BIST implementations traditionally used on SRAMs can also be applied to DRAMs; however, the read/write operations need to be redefined based on the actual PHY interface (or IOs) used in the design. The article presents and explains some of those new algorithms.
Join our online Radio Show on Friday 11th July starting at 2:00pm Eastern, when EETimes editor of all things fun and interesting, Max Maxfield, and embedded systems expert, Jack Ganssle, will debate as to just what is, and is not, and embedded system.