Etienne Racine, technical marketing engineer in the Silicon Test Solutions products group at Mentor Graphics, shares thoughts on how to apply BIST to external DRAMs in this design article on EDN.
Here’s a quote from the article’s introduction:
3D-stacked designs containing a mix of separate logic and memory die represent a somewhat new application for memory BIST (built-in self-test), compared to the more conventional, single-die embedded SRAM implementations. Gaining access to a DRAM requires predefined customized memory operations. EDA tools must make this definition step as simple as possible, while ensuring it can be reused across designs and over time. We also see that traditional test algorithms are less efficient on DRAMs, so they must be reconsidered in a 3D-IC context.
The author concludes that memory BIST implementations traditionally used on SRAMs can also be applied to DRAMs; however, the read/write operations need to be redefined based on the actual PHY interface (or IOs) used in the design. The article presents and explains some of those new algorithms.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.