Serial communication has long been an effective way of transmitting data with a minimum set of wires across long cables and different media. The serial data links that are in use vary in both transmission speeds and protocols. New serial protocols are constantly being brought to market. FPGAs with embedded SERDES blocks coupled with reconfigurable logic are effective in handling a wide range of serial communication protocols.
FPGA blocks typically embed high-speed analog SERDES blocks that work within a fixed range of data rates. Because of internal PLL operating range limitations, the lower cutoff data rate with these high-speed SERDES blocks is typically around 1,000 Mbit/s. However, there are several serial protocols that operate below that. Take the commonly used IEEE1394 protocol that extends its operating data rate from 400 Mbit/s to 3.2 Gbit/s. To support the lower data rates of such protocols, an oversampling technique can be used. In this technique, each data bit is sampled in multiple clock cycles before being transmitted. For instance, to transmit a 400 Mbit/s data rate over a serial link that supports 1 Gbit/s or above, each bit can be sampled three times and spread over three clock cycles. This is called 3x oversampling. Using this technique, lower data rates can be transmitted while the SERDES PLL continues to run within its valid operating range.
On the receiver side of the SERDES, after the clock data recovery (CDR) unit locks on to the incoming data stream and starts to recover received data, the receiver side of the logic in the FPGA looks for transitions in the received data bits. When a transition between a 1 and a 0 is initially found, the received bits from that point onward are downsampled, and the oversampled data is brought back to the original rate. In the 3x oversampling example, three consecutive 1s are downsampled to a single 1 bit, while three consecutive 0s are downsampled to a single 0 bit.
When using this technique, the CDR unit is still performing clock and data recovery. In some FPGA oversampling techniques, the CDR is providing only a high-speed sampling clock to the FPGA. The FPGA must then determine the edge boundaries of the multiple samples of bits of data. Due to the asynchronous nature of the data to the high-speed sampling clock, the oversampling must be done at least five times the data rate clock. By using the CDR unit to recover the data and create a synchronous sampling clock, the FPGA clock rate can remain at three times the data rate, thereby keeping the power down for the entire interface.
Most serial protocols use comma characters for alignment along with 8b/10b or other encoding methods. On the transmit side, the oversampling should be performed after inserting comma characters and on the encoded data stream. On the receive side, the comma detection and aligner circuits need to be employed after downsampling the received data. Such a setup is possible while using FPGAs that employ SERDES blocks with reconfigurable logic. The SERDES can be used to transmit serial data rates across wide ranges, while the FPGA logic can be used for oversampling and other functions.
Have you used these techniques or others in your designs? Please share your experiences in the comments below.