One of the fascinating things about yesterday's launch of the newest MIPS core is not the core itself. We've argued about the details of Release 5 of the MIP instruction set architecture for nearly a year now, so the microarchitecture of the first Warrior device is no real surprise.
What is very interesting is the support block that actually makes it usable in an SoC device, and this has obviously had a lot of attention paid to it.
The coherence manager combines six CPU cores with the L2 cache and I/O managers. These maintain the coherency and are a key support for the hardware virtualization. But 6 is a strange number in this binary world.
MIPS P5600 Coherence Manager (Source: Imagination Technologies)
It turns out there is a very good reason for this, and it's like your surround sound system at home. Just as you have 6 channels of sound with one bass channel for 6.1 surround sound, Imagination sees an SoC having 4.1 or 4.2 processor cores.
This would have four high performance, high clock frequency P5600 SIMD cores at 1.5GHz to 2GHz handling the heavy lifting, but burning both active power and leakage current. Alongside these cores would be one or two instantiations of the same core, but designed for low leakage and running at say 400MHz. These could be frequency scaled even further down to reduce power in a standby or monitor role while the ‘big four’ are completely switched off to prevent any leakage, giving lower system power consumption.
The absolutely key point here for Imagination is that this is the same core running the same software. This, it says, is different to ARM’s big.LITTLE approach of having a big core such as the A57 for the heavy lifting and a smaller power optimized core such as the A53 as the system controller and a lot less complex for the software developers. However, the A57 and A53 are the same ISA, so the software for the A53 runs on both, and here is little difference.
In a world where silicon truly doesn't matter, maybe there's such a case to be made. But the four cores will still be around 13sq mm if they come out 30 percent smaller than the ARM cores on 28nm -- that pits two cores totally 7sq mm against the smaller A53s, which will also burn less power in a head to head comparison on the same process with the same libraries.
What it does do is give the system architects more room within the design space, and that's always good. With the coherence manager available anyway for the hardware virtualization, that's an option that may well become popular.
However, when you start talking about the M class warrior microcontrollers with multiple cores that can be scaled up and down (because the same virtualisation hardware will be available), it becomes very interesting indeed.