Don't let temptation push you; ATE hardware isn't a place to save money.
Designing ATE hardware is one of the most difficult and time-consuming tasks involved in testing high-speed devices. Though 10Gbit/s data rates are now commonplace, serial links of 28Gbit/s and beyond bring in unique challenges and solutions. Don't take this task lightly; a simple error could cost you another 4-6 weeks on your schedule.
Careful up-front planning among all teams is necessary for success. The following steps and information is meant as a good starting place for gathering information, including some critical data that could be easily missed or overlooked. We can't possibly cover all the bases in this blog, but hopefully the information provided here will help in your adventure.
Letís start with some of the easier and more obvious requirements.
- How many lanes -- positive/negative (PN) pairs -- are needed for both RX and TX signals?
- What does the ballout look like? This is critical for determining socket escape paths.
- What socket do you intend to use?
- What is the target tester platform?
- Will this load board double as a bench board? We have had many requests for this, and it changes the project's scope in many ways.
- What are the clocks and frequencies?
- What are the jitter requirements for the clocks? EAG has had to design a dual-sub 100fs RMS tester agnostic jitter source that plugs into the ATE board to drive the 600MHz-800MHz clocks needed. We have found even the cleanest tester clock sources introduce jitter closing the eye at anything above 25Gbit/s.
- Is there a requirement for asynchronous clocks with PPM error to stress the PLLs? This is a real difficulty for ATE systems and external instruments. The above source can be used to perform this feature.
- Will the board be used to provide the cleanest signals possible, or will you need stress elements to close the eye?
- Do you need to perform any DC measurements on the channels, or is this loopback only? If that's the case, you will have to choose expensive RF relays or conical inductors for a bias T configuration.
- Does the tester have the high-speed capability to perform the measurements? This will not be applicable if it is loopback and DC only.
To Page 2: Start the design