Designing ATE hardware is one of the most difficult and time-consuming tasks involved in testing high-speed devices. Though 10Gbit/s data rates are now commonplace, serial links of 28Gbit/s and beyond bring in unique challenges and solutions. Don't take this task lightly; a simple error could cost you another 4-6 weeks on your schedule.
Careful up-front planning among all teams is necessary for success. The following steps and information is meant as a good starting place for gathering information, including some critical data that could be easily missed or overlooked. We can't possibly cover all the bases in this blog, but hopefully the information provided here will help in your adventure.
Let’s start with some of the easier and more obvious requirements.
How many lanes -- positive/negative (PN) pairs -- are needed for both RX and TX signals?
What does the ballout look like? This is critical for determining socket escape paths.
What socket do you intend to use?
What is the target tester platform?
Will this load board double as a bench board? We have had many requests for this, and it changes the project's scope in many ways.
What are the clocks and frequencies?
What are the jitter requirements for the clocks? EAG has had to design a dual-sub 100fs RMS tester agnostic jitter source that plugs into the ATE board to drive the 600MHz-800MHz clocks needed. We have found even the cleanest tester clock sources introduce jitter closing the eye at anything above 25Gbit/s.
Is there a requirement for asynchronous clocks with PPM error to stress the PLLs? This is a real difficulty for ATE systems and external instruments. The above source can be used to perform this feature.
Will the board be used to provide the cleanest signals possible, or will you need stress elements to close the eye?
Do you need to perform any DC measurements on the channels, or is this loopback only? If that's the case, you will have to choose expensive RF relays or conical inductors for a bias T configuration.
Does the tester have the high-speed capability to perform the measurements? This will not be applicable if it is loopback and DC only.
Thanks for your reply. In fact I have used IC testers myself and have written test programs and managed a sub-contractor doing the same thing! I guess what I'd call an IC tester is used to test that the IC has been made right; our ATE is used to check it's been designed right.
@jack, I tend to think of lanes in more-or-less the same way as Lance, a differential pair that makes up a transmission line. For example, a 100Gbps serial link is made of 4x25Gbps "lanes." Actually, its more like 28Gbps given overhead. In effedct, you have a parallel-serial bus.
@Jack, When I was editor of Test & Measurement World (print), I ran across the same thing. ATE means different things to different people, as we see here. At T&MW, we referred to ATE as those "big iron" testers similar to Lance's definition. But yes, I often ran into people whose definition of ATE was a bunch of instruments controlled by a PC, as you've stated.
ATE as we defined it at T&MW was usually used for testing ICs, often digital such as memory and processors.
The military uses many test stations for functionl testing where the station is made of instruments (box and modular) controlled by a PC. But, they are often called ATE. In writing about military test, I could never use ATE because our copy editors would tell me that's wrong according to our definitions.
At the time, we had two technical editors. I covered test stations according to your definition and the other editor covered ATE per Lance's definition. But then, we shared attending Autotestcon, which is all about military automated functional test, not IC test. I never understood why.
Lanes are simply P/N pairs of a transmitter, reciever or transciever or the chip itself. The article is really about the load board, system board, or evaluation board design and interface, not the actual ATE itself. Ballout is the pin out of the device(IC) you are trying to test, if you are testing a board or a subassembly this would not apply. High speed test of IC's themselves can't have IC's soldered to boards. These chips are being tested before they go into further assemblies. Certainly if you are performing board, subassembly or system level testing you would have the parts already assembled to the board instead of using a socket. The ATE's being refered o here are really what we call the semiconductor testers from companies like Advantest, Verigy, LTX, etc. It could also be a rack and stack test setup, but still targeted at the IC.
Testing our ICs using ATE is very important to our business and it always takes forever to run. So, I thought, an article about high-speed ATE looks interesting...
So, let's start with some of the easier and more obvious requirements...
- lanes? PN pairs? what?
- we find ICs perform better when they're soldered to PCBs rather than in sockets
To me ATE is a load of testgear controlled by software running on a PC. Lanes and ballout (whatever they are) don't come into it. Isn't it amazing how different two people's interpretation of something can be?
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.