Earlier this year, the folks at Altera started to pull back the curtains on their forthcoming Generation 10 FPGAs and SoCs. The idea is that Arria 10 FPGAs and SoCs will be implemented using TSMC's 20 nm process, while Stratix 10 FPGAs and SoCs will leverage Intelís 14 nm Tri-Gate process.
At that time, we learned that Arria 10 SoCs are to boast a second-generation processor system that features a 1.5 GHz dual-core ARM Cortex-A9 processor. However, the choice of processor to be deployed in Stratix 10 SoCs remained shrouded in mystery.
Well, as reported earlier today by Rick Merritt in his article Intel Makes 14 nm ARM for Altera, the veils of secrecy have been rendered asunder -- Stratix 10 SoCs are to feature a 64-bit quad-core ARM Cortex-A53 processor subsystem.
This will offer a more-than 6X throughput improvement as compared to today's currently-available highest FPGA-based processor performance from Altera, which would be the 1.0 GHz Arria SoC implemented in TSMC's 28 nm process with its 32-bit dual-core ARM Cortex-A9 processor subsystem (the Arria 10 SoC's second-generation processor subsystem implemented in TSMC's 20 nm process will boost this up to 1.5 GHz).
The Cortex-A53 offers the highest power efficiency of any 64-bit processor, wide portfolio reusability, and software compatibility with the previous generation (32-bit mode). Most importantly, the Cortex-A53's target markets overlap with those for Stratix 10 SoCs, including communications, infrastructure, enterprise, and datacenter.
One way to think about Stratix 10 SoCs is in terms of layers. First of all we have the logic layer, which is implemented in 1 GHz programmable fabric that can be used to implement custom functions such as hardware accelerators. Stratix 10 SoCs boast the equivalent of four million 4-input lookup tables (LUTs). (Note that the underlying logic modules are based on 6-input LUTs, but translating to equivalent 4-input LUTs provides a basis for comparison with other devices.)
Next we have the DSP layer, which comprises hardened floating-point DSP blocks that can provide more than 10 teraflops of computational performance in the highest end devices. On top of all of that we have the A53 processor layer.
The A53 processing layer can handle high-level tasks like load-balancing, flow control, secure boot, and FPGA configuration and power management. The DSP layer can be used for floating-point computations, matrix manipulations, and waveform processing. The logic layer can be used to implement functions like deep packet inspection, hardware acceleration, and special cryptographic engines.
The bottom line is that this is very exciting news. Equipped with 64-bit quad-core ARM Cortex-A53 processor subsystems, Stratix 10 SoCs look set to be a game-changer with regard to using FPGAs in extreme-performance applications.
-- Max Maxfield: Editor of all things fun and interesting!