It looks as if the "Big Three" EDA vendors are gearing up for the next battle to capture the SoC verification market.
I recently attended Cadence-Live in Bangalore to learn about the latest and greatest in verification technologies. As expected, many of the sessions were geared towards System-on-Chip (SoC) verification using formal and simulation techniques. The main draw was the hardware-assisted (HA) verification session track. Yes, I use the word "hardware-assisted" since the word "emulation" is overloaded, confusing, and a misnomer.
It looks as if the "Big Three" EDA vendors are gearing up for the next battle to capture the SoC verification market. Hardware boxes such as Palladium have been around for years. So, why the sudden buzz? My take? Two factors as follows:
- The SoC verification domain has been in need of simulation horsepower with increasing integration of Intellectual Properties (IPs). Traditional software-based simulation, which has been the bulwark of verification, restricts what you can run and how much you can run on your design-under-test (DUT). Simulation time and memory has always been the Achilles heel for simulators. With short time-to-market (TTM) and stringent margins, verification folks don't want to wait for days for system-level simulation to generate results. The current ballpark figure for simulation speed is about 4MHz on these boxes.
- The latest breed of Verification IPs (VIPs) meant for these boxes -- referred to as Accelerated VIPs (A-VIPs) -- with their UVM/OVM interfaces, makes it appealing for verification folks in look-and-feel with respect to traditional VIPs.
My take is that the SoC verification folks will embrace the A-VIP approach with these boxes as long as testbenches don't require massive rework between software-based and HA-based simulation. Of course, not all is rosy on this path; RTL compilation time, debug, and coverage are upcoming challenges to be solved. Now that HA-based verification is on the rise at the SoC level, will it translate to the need for more low-level software running on the DUT during verification? This would translate to shorter SoC realization time (the time required to integrate the hardware and software).
If HA-based techniques show promise in reducing verification time for SoC integrators, then another avenue to reduce integration time is to demand production-worthy software drivers from IP vendors. As many of you may recollect, a decade back, SoC vendors like TI and Intel were hardly bothered about the software needs of an OEM vendor. An OEM vendor had to align with a software development firm or groom their team to create the necessary stack and applications. With short TTM coupled with intense market pressures and margins, SoC vendors bent over backwards and started to provide the necessary stacks and software development kits (SDKs). Pressure from market forces -- from OEM vendors to SoC integrators -- can be seen as a ripple effect in the software supply chain.
With IPs becoming increasingly complex, programmable SoC integrators will expect IP vendors to provide production-worthy software drivers and other abstractions to reduce the time required for software integration and realization. With some of the latest software stacks -- like those used in Audio-Video Bridges (AVBs) -- requiring certification of the underlying Ethernet-IP and software combination, IP vendors will have a lot to deliver and package going ahead (see also Essential Abstractions).
Is this a foreshadowing that IP vendors will soon be investing in HA verification boxes for verification and software development?