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Tips & Tricks: Creating a 2W+4R FPGA Block RAM, Part 1

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Brian_D
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ICE40 multiport examples
Brian_D   11/13/2013 8:30:25 AM
This was discussed briefly on the Programmable Planet a couple months back, in the context of building a [1W+2R] memory from the "simple dual port" [1W+1R] block RAMs that are available in the Lattice ICE40 family.

I would post a direct link, unfortunately the Programmable Planet was recently destroyed by the UBM division of the Vogon Constructor Fleet in order to make way for a new subspace billboard.

As of the moment, Google has a cached copy of the thread here:

http://webcache.googleusercontent.com/search?q=cache:nqd_1zUR4bkJ:www.programmableplanet.com/messages.asp%3Fpiddl_msgthreadid%3D271824%26piddl_msgorder%3Dasc+&cd=1&hl=en&ct=clnk&gl=us&client=firefox-a

In the event that vanishes, FWIW the ICE40 [1W+2R] code example can be found here:

http://code.google.com/p/yard-1/source/browse/trunk/hdl/systems/evb_common/block_ram/lattice/rtl_mem_ice40.vhd

-Brian

hamster_nz
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Just at the right (write?) time....
hamster_nz   11/13/2013 4:05:45 AM
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Hi Alvie,

Just stumbled over this on twitter (#FPGA) - making use of this right now.

I resolved the conflict a cruder way - the addresses are compared, and if they match then the datain is registered to place on the dataout of the other port, and the enable of the read port is inhibited (don't know if I explained that correctly or not!).

However, this way is much cleaner.

 

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