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Tips & Tricks: Creating a 2W+4R FPGA Block RAM, Part 1

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Brian_D
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Re: ICE40 multiport examples
Brian_D   11/15/2013 7:57:42 PM
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@Alvie "This is the first part of the artice. The second part will deal with adding an extra write port to the design"

Hopefully I haven't disrupted the natural order of the blog series in replying to Karl's post ( which I might have misunderstood anyway ).

Perhaps not obvious from my original post here, but the intent of the earlier APP link was to cover some practical issues ( synthesis directives & coding styles ) needed to successfully infer a "replicated" multiport structure with Synplify in an FPGA target having only Simple Dual Port RAM.

-Brian

Alvie
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Re: ICE40 multiport examples
Alvie   11/15/2013 11:13:05 AM
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@Brian_D: This is the first part of the artice. The second part will deal with adding an extra write port to the design.

Regarding the multipumping you're speaking about in order to get a second write port is also possible. I'll address that option as well.

Alvie

Alvie
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Re: Number and Types of Ports
Alvie   11/15/2013 11:10:03 AM
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@DrFPGA: Indeed, you are correct. It was a typo on my part. The memory will have four read ports and two write ports. Thanks for pointing that out.


Alvie

DrFPGA
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Number and Types of Ports
DrFPGA   11/15/2013 11:01:54 AM
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In your first paragraph you say: 

I will explain the path from a normal FPGA Block RAM into a 2W+4R (two read ports and four write ports) memory, which I needed for my upcoming CPU design.

Should that be two "Write ports and 2 Read ports"?

Brian_D
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Re: ICE40 multiport examples
Brian_D   11/14/2013 8:28:50 PM
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@Karl "This is not the same as using 2 simple dual ports.  There both RAMs must be written every time to maintain integrity."

It is unclear to me exactly what you are disagreeing with.

My earlier post, here on EET, explicitly stated [1W+2R] :

"in the context of building a [1W+2R] memory from the "simple dual port" [1W+1R] block RAMs that are available in the Lattice ICE40 family."

Which is exactly what Álvaro is building in his second figure ("2R+1W block RAM") in the above article.

I would agree that Álvaro's first figure, a TDP with write collision logic, uses a different approach.

"I think there is no way to make a true dual port using 2 simple dual ports because for writes both addresses have to be the same."

 My earlier posts on the late Programmable Planet thread did mention running SPD(s) at 2x the clock rate to get two write ports from a simple dual port.

-Brian

KarlS01
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Re: ICE40 multiport examples
KarlS01   11/14/2013 3:57:38 PM
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@Brian:  This is not the same as using 2 simple dual ports.  There both RAMs must be written every time to maintain integrity.

In this case is special because true dual port can write one port and read a different address simultaneously on the other port.  The write to the second port is a write thru only if the addresses are the same.

Therewfore I think there is no way to make a true dual port using 2 simple dual ports because for writes both addresses have to be the same.

hamster_nz
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Resistance is tasty!
hamster_nz   11/13/2013 10:15:14 PM
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Since we are off topic - resistance is tasty! - A gingerbread amplifier.

Gingerbread Amp

http://www.adafruit.com/blog/2012/12/28/gingerbread-class-ab-amplifier/

 

Alvie
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Re: Resistance is useless!
Alvie   11/13/2013 3:04:00 PM
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Resistance is by no means useless!

You should join the resistance perhaps...

Join the resistance

betajet
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Resistance is useless!
betajet   11/13/2013 1:09:36 PM
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Uprated for reference to Vogon Constructor Fleet :-)

Brian_D
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ICE40 multiport examples
Brian_D   11/13/2013 8:30:25 AM
This was discussed briefly on the Programmable Planet a couple months back, in the context of building a [1W+2R] memory from the "simple dual port" [1W+1R] block RAMs that are available in the Lattice ICE40 family.

I would post a direct link, unfortunately the Programmable Planet was recently destroyed by the UBM division of the Vogon Constructor Fleet in order to make way for a new subspace billboard.

As of the moment, Google has a cached copy of the thread here:

http://webcache.googleusercontent.com/search?q=cache:nqd_1zUR4bkJ:www.programmableplanet.com/messages.asp%3Fpiddl_msgthreadid%3D271824%26piddl_msgorder%3Dasc+&cd=1&hl=en&ct=clnk&gl=us&client=firefox-a

In the event that vanishes, FWIW the ICE40 [1W+2R] code example can be found here:

http://code.google.com/p/yard-1/source/browse/trunk/hdl/systems/evb_common/block_ram/lattice/rtl_mem_ice40.vhd

-Brian

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