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Invensas Zeros In on 3D IC Realities

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sarkalgud
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Reducing capacitance
sarkalgud   11/22/2013 1:40:53 AM
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Herb is probably tied up with the interposer workshop at GIT, so I'll jump in - Simon's point was that the world is going to 3D IC, which means using vertical interconnects/Through Silicon Vias to connect stacked chips. Using TSVs decreases line lengths significantly, and this is where the decrease in resistance and capacitance occurs.   

chipmonk0
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Re: " ... minimizing interconnect length and capacitance, as well as offering very broad buses, .. "
chipmonk0   11/19/2013 10:32:48 AM
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this article seems to be an Orphan. still no response from the author !

chipmonk0
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Re: " ... minimizing interconnect length and capacitance, as well as offering very broad buses, .. "
chipmonk0   11/16/2013 1:18:33 AM
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shortening interconnects is the rather obvious way but not easy. I was actually waiting for a reply from the author himself since he might have more specific information. 

Astronut0
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Re: " ... minimizing interconnect length and capacitance, as well as offering very broad buses, .. "
Astronut0   11/15/2013 7:12:16 PM
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Reducing wire length automatically reduces capacitance.  There may be other ways to influence capacitance, but wire length is the big one.

chipmonk0
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" ... minimizing interconnect length and capacitance, as well as offering very broad buses, .. "
chipmonk0   11/15/2013 12:05:26 PM
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So what is being done to minimize interconnect Capacitance ? Who is doing it ?

Deepak1982
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Nice article
Deepak1982   11/15/2013 7:09:48 AM
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Good to see you writing on EETimes, Herb... looking forward to your next article.

- Deepak Sekar, Rambus.

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