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3D Stacks Need Lower Costs, Broader Backing

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Re: 3D Stacks Need Lower Costs...
chipmonk0   11/27/2013 2:24:20 PM
It is premature to talk about cost because there are performance issues with the mainstream implementation of 3d stacks with TSVs.

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Re: 3D Stacks Need Lower Costs...
HerbR0   11/26/2013 10:13:22 PM
MP, Thanks for your frequent comments! My primary concern is that the packaging experts can only compare COMPONENT cost of 2.5/3D-ICs versus the traditional, and until now save approach of following Moore's Law. That's why we are stuck at this "cost problem".

In my 20+ years in the ASIC business I saw the real breakthrough of ASICs when 1) system designers realized the opportunity of increasing system speed, lowering power and boardspace and 2) worked, together with their IC designers and the ASIC design center engineers on re-architecting their systems  and 3) last, but not least, convinced management to approve significant budgets to pay ASIC NREs.

As an eternal optimist, I am continuing to encourage our industry's decision makers to recall their experience with the transition from 7400 logic to ASICs and make the right decision again. 

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Re: 3D Stacks Need Lower Costs...
docdivakar   11/26/2013 6:16:19 PM
Herb, it looks like the momentum we expected has not yet materialized. Without a lower cost manufacturing alternative, 3D stacks will remain a play for bigger companies with the purse to fund the projects and more agile smaller players will be left out. Your line "how many IC designers were in the audience..." says a lot about the status of design engineers embracing and realizing the potential to develop products in 3D.

MP Divakar

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