In this installment of our 3D IC mini-series, we ponder the current state-of-the-art 3D IC technologies.
Traditional 2D ICs/SiPs
Now, this is where things can start to become a little tricky if we aren't careful, so let's take this part of our discussions step-by-step. In fact, let's begin by taking a step back and reminding ourselves that -- in the case of a traditional 2D IC/SiP -- the die or dice are mounted in the package in a single plane. The reason I say "dice" is that a traditional 2D implementation may contain multiple chips as shown below:
A traditional 2D IC/SiP.
For the sake of simplicity, we are showing only two dice in the SiP, but -- of course -- there could be many more. Also, in this illustration we are assuming that the dice are mounted on the SiP substrate using flip-chip technology (wire-bond technology could also be used). In this case, the flip-chip solder bumps will be ~100μm in diameter.
Let's also assume that the SiP substrate is of the laminate variety. That is, a small, fine-line printed circuit board with copper tracks and copper vias containing a number of tracking layers. Although this form of SiP technology really is incredibly impressive, the tracks on the SiP substrate are orders of magnitude larger than the tracks on the silicon dice. This discrepancy in size impacts performance and power consumption. Also, the larger tracks on the SiP substrate lead to routing congestion that places limitations on the number of die-to-die connections that can be realized.
Active-on-passive 3D ICs/SiPs with TSVs
The next step up the complexity ladder is to place a silicon interposer between the SiP substrate and the dice. As shown in the illustration below, the silicon interposer has through-silicon vias (TSVs) connecting the metallization layers on its upper and lower surfaces:
Active-on-passive 3D IC/SiP using a silicon interposer and TSVs.
Some people refer to this technology as "2.5D" on the basis that the silicon interposer is passive -- that is, the interposer does not carry active components like transistors. Having said this, it's also not uncommon to refer to this as "active-on-passive 3D IC/SiP" technology.
In this case, the dice are attached to the silicon interposer using micro-bumps, which are ~10μm in diameter. Meanwhile, the silicon interposer is attached to the SiP substrate using regular flip-chip bumps, which will be ~100μm in diameter. The tracks on the silicon interposer's topside and backside metal layers (there can be multiple metal layers in both cases) are created using the same processes as the tracks on the silicon chips.
Although the silicon interposer and the silicon dice in the image above appear to be a little chunky, you have to remember that this drawing is not to scale. In reality (as we discussed earlier in this column), the dice -- and the silicon interposer -- may be only ~0.2mm to ~0.7mm thick.
As one example of the use of this technology, the Xilinx Virtex-7 2000T device has four FPGA dice attached to a silicon interposer, which supports ~10,000 silicon-speed connections between adjacent dice.
The advantage of using active-on-passive 3D IC/SiP technology is that it's an incremental step from traditional 2D IC/SiP technology that offers tremendous increases in capacity and performance. There are also yield advantages, because it's easier to make a number of small dice as opposed to a single large one. The main disadvantage is that it's non-trivial to make all of this work. ("If it were easy, everyone would be doing it," as the old saying goes.)
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