In this installment of our 3D IC mini-series, we ponder the current state-of-the-art 3D IC technologies.
In my previous column on the topic of 3D ICs, we pondered what the world used to be like before the dawn of these little rascals, including the use of lots of small, individually-packaged dice, the advent of system-on-chip (SoC) devices, and the introduction of system-in-package (SiP) assemblies.
In this column, we will consider the various forms of 3D IC technology, starting with the simpler incarnations and culminating in today's start-of-the-art implementations.
Simple stacking technologies
When we start to talk about 3D (three dimensional) ICs, the first thing we have to ask ourselves is, "What exactly do we mean by 3D?" As we shall see, this is not as trivial a question as it may first appear, because "3D" may mean different things to different people. For example, one early form of 3D IC technology -- which is still in use to this day for certain applications -- is to take a group of dice that all perform an identical function (like memory chips, for example), to build them into a 3D stack, to run connecting wires down the sides, and to present the resulting assembly in the form of a system-in-package (SiP):
3D die stack with connecting wires running down the sides.
Although the diagram above gives the appearance of being tall, thin, and ungainly, it's important to remember that each of the silicon die will be ~0.7mm thick (this may be reduced to only ~0.2mm thick if a back grinding process is used to thin the wafer).
Another approach that is commonly used is to mount one die on the SiP substrate using flip-chip technology, and to then mount a second die on top of the first using wire-bond technology as shown below:
A simple form of 3D IC/SiP.
Now, both of the technologies discussed above are very clever, but they really aren't what I think of when someone says "3D" in the context of integrated circuits. For that, we have to move to the next level…
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