Breaking News
Blog

Monolithic 3D IC Technologies

NO RATINGS
1 saves
Page 1 / 2 Next >
View Comments: Threaded | Newest First | Oldest First
Max The Magnificent
User Rank
Blogger
If this technology becomes mainstream...
Max The Magnificent   12/2/2013 3:02:12 PM
If this technology eventually becomes mainstream, it will really change things -- this truly is a 3D IC technology -- I'd love to hear from someone who has used it to make a real chip...

Garcia-Lasheras
User Rank
Blogger
Thermal issues on 3D ICs
Garcia-Lasheras   2/14/2014 11:07:50 AM
NO RATINGS
This is a very interesting column, Max. Your explanation about the physical processes involved in building this kind of 3D ICs is very clear and enlightening.

But I've a question for you. One of the main issues with 3D ICs is how to get rid of the extra heat that is produced inside the "dice". I've heard that a very promising alternative is embedding active cooling devices into the IC -- e.g. Peltier towers. Do you have any clue about this?

Max The Magnificent
User Rank
Blogger
Re: Thermal issues on 3D ICs
Max The Magnificent   2/14/2014 11:13:59 AM
NO RATINGS
@Garcia: One of the main issues with 3D ICs is how to get rid of the extra heat that is produced inside the "dice". I've heard that a very promising alternative is embedding active cooling devices into the IC -- e.g. Peltier towers. Do you have any clue about this?

Sadly not -- but I'm sure the folks at MonolithicIC3D do. I will "ping" them and ask them to comment here.

Max The Magnificent
User Rank
Blogger
Re: If this technology becomes mainstream...
Max The Magnificent   1/16/2014 11:24:53 AM
@rahul28feb: i have some brief information about the 3D ICs market...

Wonderful -- thanks for sharing

Or_Bach
User Rank
Rookie
Heat Removal from monolithic 3D IC device
Or_Bach   2/14/2014 11:48:27 AM
NO RATINGS
Heat removal is a known issue and important one. The advantage of the monolithic 3D stacked device is that all upper layers are thin and not too far from the base wafer bulk or from the upper surface of the device. In IEDM 2012 we had published joint work with Stanford University showing that the heat could be very effectively be removed using the power distribution network (PDN). The work was also covered by a follow on blog: http://www.monolithic3d.com/2/post/2012/12/can-heat-be-removed-from-3d-ic-stacks.html

Max The Magnificent
User Rank
Blogger
Re: Heat Removal from monolithic 3D IC device
Max The Magnificent   2/14/2014 11:54:40 AM
NO RATINGS
@Or_Bach: In IEDM 2012 we had published joint work with Stanford University showing that the heat could be very effectively be removed...

Great feedback Zvi, thanks for responding so quickly

Garcia-Lasheras
User Rank
Blogger
Re: Heat Removal from monolithic 3D IC device
Garcia-Lasheras   2/14/2014 3:17:18 PM
NO RATINGS
Or_Bach: "the heat could be very effectively be removed using the power distribution network (PDN)"

Thank you very much for this valious update. The blog you are pointing out is really interesting. So, you reuse the Power Distribution Network in the same way some heat sinks use heat pipes -- but immersed into the "dice". Is this right?

Or_Bach
User Rank
Rookie
Heat removal
Or_Bach   2/14/2014 3:45:21 PM
NO RATINGS
Yes, copper is a good heat conductor and there is a general need to have a good power delivery which imply use of thick copper wires across the device with many vias to spread the power across the device. 

In monolithic 3D we can have many vias which provides good heat transfer from the inner transistors layers to the device heat-sink. And the very thin layers of monolithic 3D means that the distance from where the heat is being generated to where it could dissipate is only few microns. Accordingly the power-distribution-network could be used to effectively removed the inner heat.

It should be noted that monolithic 3D is most effective way to reduce the overall heat generated in IC device as it significantly reduce the average interconnect length.

 

chipmonk0
User Rank
CEO
Re: Heat removal
chipmonk0   2/14/2014 4:11:51 PM
NO RATINGS
There seems to be some usual confusion going on here between 3-d stacking of dice ea. first processed separately on separate wafers to build device ( the original question by Lasheras ) and devices built one on top of another on the same wafer ( in the response by Zvi ).

in the first case the thermally conductive Cu used to fill the through vias can aid vertical heat dispersal but not completely since they also introduce stress if placed too close to the transistors. the TSVs do nothing to directly aid lateral heat dispersal. IBM / 3M and a few others are working on this part as local heat build up impacts memory refresh times.

For the second config. of 3-d, which Zvi has been championing for a while, what are the vias between transistors built one on top of another made of ? Copper or still much less conductive Tungsten ? Samsung's 3-d NAND sticks to usual CVD W. But as Zvi says, the heat transfer distances are within microns and so the fluxes could be acceptable even with vias filled with CVD W which has a k just a quarter of Cu.

Flash Poll
Radio
LATEST ARCHIVED BROADCAST
Join our online Radio Show on Friday 11th July starting at 2:00pm Eastern, when EETimes editor of all things fun and interesting, Max Maxfield, and embedded systems expert, Jack Ganssle, will debate as to just what is, and is not, and embedded system.
Like Us on Facebook

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Times on Twitter
EE Times Twitter Feed
Top Comments of the Week