A handy rule of thumb to determine if an interconnect trace should be considered a transmission line is if the interconnect delay is greater than 1/8th of the signal transition time, it should be considered a transmission line and afforded all of the attention required by a transmission line.
Often, for more complex systems, you can break it down some, and choose the "prime" frequencies - it will often be that much of the equipment uses similar frequencies, and you can throw these into your plan as well. But you are correct - this can get onerous - and in those cases, you likely just have to use your best judgement and also lean on the experts that are working your grounding/shielding to tell you which frequencies will likely be the worst problems.
>Of course, there are cable grounding and shielding issues. The most significant is to make a 360° connection with a shield around a connector.
And make the shield connection to the chassis, not digital ground. I once had to clean up a horrendous mess where the designer connected coaxial cable shields to his pcb digital ground plane and could not understand why the radiated emissions were so strong.
"coming from the days of much slower clocks and signals"
I won't comment on Max's slower days, but another issue is power supply clock frequencies, especially when high-speed digital links are involved. power supply or other clock frequencies can couple into digital clocks, creating periodic jitter. The higher the clock rate, then less jitter it takes to ruin signal integrity.\
Signal integrity engineer Daniel Chow explains periodic jitter in Jitter: Measurement References Matter. The animated graphics really bring it to life. The article has links to numerous other articles covering jitter.
When performing an emissions test, you usually want worst case and thus many systems have diagnostic software for the purpose of emissions testing. It would be like exercising more FPGA gates than are used in normal operation. Or you might drive a a whole lot of gates at once for a worst-case condition.
Also with regards to FPGAs, another test is to drive as many gates as possible all at once for testing power integrity on a board. That causes the FPGA to draw maximum current so you can see what it does to the power rails due to inductance in the power delivery network. Too deep a dive in power can cause havoc and you probably need better or more bypass capacitors on the board.
Display's also radiate -- CRT's were kind of bad with the magnetic deflection, and the new LCD, etc displays scan the array to update it -- this means that there are effectively long rows of horizontal and vertical ITO traces being switched on and off to make each pixel light or dark -- and ITO must be placed over the whole array to reduce these emmisions -- DO-160 is often hard to pass, for a display designed only to pass FCC/CE