Like the perfect temperature at which beer should be served, asking questions about the design and location of a decoupling capacitor network will return different answers depending upon who is being asked. The funny thing is that, even though the answers may be very different, each respondent will be sure that only he or she is correct.
Before I discuss my preferred beer temperature and how I design and locate my decoupling capacitors, I think it is important we all understand why we have decoupling capacitor networks in the first place. These networks are intended to perform two functions: to provide a low-impedance path to ground for AC signals and noise signals superimposed on the DC supply voltage, and to act as a local energy store close to the device being decoupled, so that high-frequency demands for current (due to logic gates switching, for example) can be supplied without affecting the voltage rail. Remember that a power supply has a much slower response time to transient demands than the operational speed of the devices it powers. At higher frequencies, on-chip decoupling is required, but that's a story for another day.
Both of these requirements will have bearing on the design of the decoupling capacitor network. We must also understand the parasitic elements and construction of a real-world capacitor, which -- along with its capacitive element -- will have resistive and inductive elements, as illustrated below.
Real structure of a capacitor (for decoupling purposes,
RP is normally discounted).
Equivalent series resistance (ESR) is defined by the resistance of the leads or pads and losses in the dielectric. This is typically in the range of 0.01 to 0.1Ω for a ceramic capacitor.
Equivalent series inductance (ESL) is defined by internal connections or leads and pads. This is very important in the case of decoupling, because it will dominate over the capacitance above certain frequencies.
From the model above, it is clear that the capacitor C and the ESL will form a series resonance creating a near short (it is not a dead short, due to the ESR). You can calculate the self-resonant frequency (SRF) of a capacitor using the following equation.
Equation for self-resonant frequency (SRF) of a capacitor.
What this means is that, if you have a specific AC frequency you wish to remove, you should ideally select a capacitor with a SRF at the relevant frequency. Another consideration is to ensure a low-impedance profile over a wide frequency band, which will require a range of capacitor values connected in parallel. For example, the network illustrated below employs two different value capacitors. Observe that there are more lower-value capacitors than higher-value ones.
An example decoupling capacitor network (click here for a larger version).
When you are calculating this, do not forget the contribution of PCB interplane capacitance, which will dominate at high frequencies. Interplane capacitance is achieved by careful design of the PCB stack to ensure that the power and ground planes are closely coupled within the stack, thereby creating capacitance.
It's important to remember that the combined decoupling impedance is a function of all the different types and quantities of decoupling capacitors. The example below shows a combined decoupling capacitance (dark blue) formed using 100nF capacitors (pink), 10nF capacitors (yellow), and 11µF capacitors (cyan/turquoise). In this case, the combined decoupling impedance is required to be below 0.1Ω across a wide frequency range.
Decoupling impedance, which must be below 0.1Ω across a wide frequency range (click here for a larger version).
Your target impedance will be defined by the parameters of the voltage supply being decoupled, the maximum transient current, and the allowable ripple on the rail, as described by the following equation.
Equation for target impedance for a decoupling capacitor network.
Having defined the target impedance, you can then use the capacitors available to you and their supplied information -- capacitance, ESL, ESR, tolerance, and drift -- to design a network that meets your impedance profile.
Your selection of decoupling capacitor will generally involve a ceramic device -- commonly a multi-layer component -- although polymer capacitors may be used for some applications. When it comes to selecting the most appropriate device, obviously you will start by looking for a low ESR and an acceptable SRF. You will also need to understand how the capacitor will operate across the desired temperature range and, more importantly, how the capacitance will change with temperature. For example, an X5R capacitor will work between -55 and +85°C with a change in capacitance of ±15% across the temperature range. A Y7V capacitor will operate between -30 and +125°C while exhibiting a variation of +22 to -82% of capacitance value. Selecting the correct type is crucial.
Please remember to follow any recommendations made by the chip manufacturers. Some devices have on-chip decoupling, which reduces the board-level decoupling requirements. The reasons for this will become clear in my next column in this miniseries.
Based on the discussions above, your decoupling network should now acknowledge the parasitic elements and component tolerances of the various capacitors you've selected. Sad to relate, however, this does not guarantee the final performance of the network. This is because we have not yet taken into account any parasitic parameters associated with the component mounting, nor have we considered the effects of component placement. Both will have a significant effect upon the performance. I will address this next time. In the meantime, I prefer my beer ice cold, and I think I need one now.