When we left my previous blog on the topic of decoupling, we were well on the way to understanding the behavior of a real capacitor, the temperature at which I like my beer, and how to go about designing a decoupling capacitor network. What we had not addressed was the somewhat tricky aspect of where our decoupling capacitors should be located.
Whenever I talk to people about decoupling, they all say that the capacitor should be placed as close to the device as possible. However, very few people can actually tell me why this is or at what point close enough becomes too far away. As engineers, we need to understand what drives the placement of these components. Using this knowledge, we can define a series of rules regarding placement and layout such that the layout engineer is not told simply to put them as close as possible. The lack of clear guidance can hurt the complexity of the design, the complexity of the manufacturing, and the cost of the circuit board.
A key aspect of decoupling is controlling the inductance associated with both the tracking and the mounting of the capacitor. Though the capacitor stores the charge, the inductance determines the speed at which this charge can be delivered from the capacitor. Therefore, reducing the inductance loop is the most important aspect to consider when placing a capacitor.
This starts with the very design of the surface mount technology capacitor mounting pads within your PCB library. Ideally, the mounting via should be located as close as possible to the pad (though not within the pad, unless you are using micro-via technology). If space permits, it is better to use multiple vias per pad to reduce overall inductance. You definitely do not want long, thin tracks from the solder land to the via. Also, do not be tempted to share vias between capacitors.
The inductance loop is defined as the loop created between the mounting via and the connections to the voltage planes. For this reason, when you define the stack of your board and assign layers to power and ground, you need to assign higher-priority power planes (those with higher current demands from the device being decoupled) to be higher in the stack. This reduces the vertical distance the current needs to travel before reaching the plane.
When implemented correctly, the mounting inductance will be similar in value to the equivalent series inductance. This will have an impact on the resonant frequency (RF) of the capacitor, so it should be included in the RF calculation. As the inductance increases, the RF -- not the self-resonant frequency, because the mounting inductance is included -- will be reduced.
Once calculated, the RF for the mounted component tells us the frequency at which the capacitor is most effective. Thus, we can use this to determine how close the capacitor needs to be located to the device it is decoupling to be most effective.
As the device being decoupled demands more current, it will cause a disturbance in the local power plane. The decoupling capacitor will attempt to counteract this. There is a finite time between the device demanding current and the capacitor sensing and acting on the demand. The time delay is calculated as follows.
You can determine the signal propagation speed in your circuit board by the following equation (where εr is the dialectic constant of the PCB material).
It obviously takes the same time delay for the current supplied from the capacitor to reach the device; hence, there is a round-trip delay. We can therefore use the propagation speed Vp to determine the effective wavelength of the capacitor at its mounted RF. This wavelength can then be used to determine how close to the device being decoupled the capacitor needs to be placed using the following rules:
- When the capacitor is located more than a quarter of a wavelength away, the capacitor has no effect on the device being decoupled.
- The energy transfer will increase the closer the capacitor is located to the device being decoupled.
- An ideal target is to place capacitors within 1/40th of a wavelength. This means that smaller value capacitors have to be placed closer than larger ones.
You can calculate the wavelength of the capacitor using the following equation.
As we noted above, it's good practice to locate the decoupling capacitors within 1/40th of the wavelength, which means you will have zones of decoupling, as shown below.
Priority should be given to termination resistors and discrete filtering capacitors for things like high-speed serial link power supplies over decoupling capacitors close to the device.
So now we understand the reasons we decouple and how we go about doing this on the final design, including the rules outlining the placement of our decoupling capacitors. It is possible to verify the final layout using tools like HyperLynx Power Integrity from Mentor Graphics, which will look not only at DC drops across planes (this is just as important as decoupling), but also at the AC performance. Any questions?