Most speakers at the recent 3D Architectures for Semiconductor Integration and Packaging (3-D ASIP) event expressed optimism that materials, equipment, and manufacturing flows are ready for interposer-based 2.5-D designs. Many prototypes and evaluation units are in progress, with very positive reliability test results shown in a number of presentations. In addition, Hynix and Tezzaron presented their memory stacks using through silicon vias for boosting memory access by mounting these devices side-by-side with CPUs on an interposer.
Only a few presenters attached specific dates to their roadmaps -- a clear sign that the market pull for this technology is not in full swing yet. Most likely customers are still analyzing 2.5-D benefits and cost savings on the system-level before engaging on a broader scale. In private discussions, last week’s presenters labeled 2014 as the year of many design-ins and 2015 as the year of production ramps for interposer-based designs with 3-D memory stacks. These predictions may prove to be too conservative considering Samsung’s successful Exynos processor is already using Wide I/O technology in production.
Doug Yu from TSMC explained that traditional CMOS metal-pitch scaling, a key determinant of die size and cost, is slowing down. By contrast, TSMC's CoWoS chip-stacking technology, with its 20-micron pitches, enables significant form-factor reduction, shorter interconnect lengths, and much lower capacitance compared to designs using BGAs with 250-micron ball pitches mounted on PCBs, he said. TSMC is developing larger interposers, and expects unit costs to come down as volumes increase and equipment depreciation decreases, he suggested.
In one of the more interesting talks, Joseph Maurer outlined a variety of ongoing DARPA-funded programs working with several partners in industry and academia to enhance intra- and inter-chip cooling, one of the chief hurdles of 3-D stacks. Separately, Georgia Tech outlined efforts to enhance cooling for and reliability of vertically stacked dies in chip stacks.
Robert Patti described Tezzaron’s 3D-RAM architecture. It implements I/O circuits, sense amps, and the actual memory cells with access transistors in separate, vertically stacked dies. The architecture introduces new levels of modularity and flexibility. It improves performance, power dissipation, redundancy, management, and testability.
AMD’s Bryan Black explained from a system-level and cost perspective why chip stacks will replace continued feature-size shrinking in the next several years. He also described the benefits of SK Hynix's High-Bandwidth Memory (HBM) for graphics applications.
Minsuk Suh of SK Hynix showed very positive reliability test results for HBM devices. He also presented schedules, demonstrating Hynix provided samples of its 64 GB LRDIMM module to customers earlier this year.
Semtech’s Craig Hornbuckle reported on a joint development project with IBM for a high-speed networking application. The companies integrated a 45-nm CMOS logic die with two SiGe dies, coming from different fabs, on an interposer. He described the high bandwidth between the three dies, the low insertion loss and the excellent SNR, and other benefits of the device.
Kazuki Fukuoka from Renesas described work on a 3-D test vehicle, combining a logic die and a 4 Gbit Wide I/O DRAM using through silicon vias. The device reduced I/O power 89 percent compared to discrete chips.
In other talks, Arif Rahman stated that Altera will use die stacking in its Stratix 10 products, manufactured in Intel’s 14-nm technology. Teledyne’s Miguel Urteaga said chip stacks integrating III-V materials with silicon will offer performance and power benefits in very high frequency applications.
Yervant Zorian, a test expert at Synopsys, showed how the company's design tools enable testing of chip stacks. They use boundary-scan and test-wrappers -- as suggested in IEEE P1838 -- to access digital circuitry in every die of a stack and deploy BIST engines to test analog blocks.