The integrator's task
The integrator needs to ensure that the integration they create between all these IPs does not create new signoff problems. How might such a problem be possible if all the IP are clean? Just a few of the possibilities are:
- Creating a combination loop through unregistered paths in IPs
- Failing a synchronization requirement which the IP assumes will be handled at integration
- Using an IP in a configuration which was not qualified and which has a previously unknown issue in that configuration
- Having IP with an input port assumed to be driven with slower clock but connected to faster clock source at the chip level
Analysis and signoff at this level cannot be skipped. But it can be greatly simplified. First, it is important to signoff and abstract IPs in the target configuration, if this was not already done by the IP provider. The abstraction step is significant. Without this, analysis is feasible but may take longer, both in run-time and analysis/debug time to bypass "don't care" issues inside the IP. As design size approaches those billion gate levels, hierarchical analysis based on abstractions becomes an important consideration.
To understand how this works, consider the example illustrated in below.
If you (or an IP provider) have already performed block level handoff analysis of MEM_block, DSP_block, and POWER_CONTROLLER blocks, there is no reason to repeat their analysis during SoC integration (shown on left). A more efficient way is to abstract (grey-box) the results from the block analysis and make it available to SoC analysis so the SoC analysis focuses on the SoC level issues alone (Shown on right side of image).
It is important to understand that this is not the same as black-boxing the blocks. If the SoC analysis had no insight into the block analysis performed already, SoC analysis would be inaccurate. The abstraction represents an accurate model of the blocks analyzed, so the SoC analysis is accurate yet doesn't need to load all the design data of those blocks.
We can understand how these abstracted models enable an accurate, yet faster and more efficient analysis of the SoC through an example. Suppose there are combinational paths in blocks A and B. In a hierarchical SoC methodology, after the block level analysis, there will be abstracts created for each block which will record the combinational path.
Combinational paths in blocks A and B