Breaking News

Doing Math in FPGAs, Part 3 (Floating-Point)

4 saves
Page 1 / 2 Next >
View Comments: Newest First | Oldest First | Threaded View
<<   <   Page 3 / 3
Max The Magnificent
User Rank
Signed magnitude
Max The Magnificent   1/7/2014 4:24:53 PM
Hi Tomii -- as you point out, the sign-bit in the IEEE 754 is just 0 = positive, 1 = negative; that is, the combination of the sign bit and the mantissa is a sign-magnitude vale as opposed to being a two's complement value. One problem with thsi is that you can have both +0 and -0 values. Have you any idea why they chose to do things this way?

<<   <   Page 3 / 3
August Cartoon Caption Winner!
August Cartoon Caption Winner!
"All the King's horses and all the KIng's men gave up on Humpty, so they handed the problem off to Engineering."
Top Comments of the Week
Like Us on Facebook Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Times on Twitter
EE Times Twitter Feed
Flash Poll
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.