How exciting! I just took delivery of my very own ZedBoard -- a low-cost development board for the Xilinx Zynq-7000 All Programmable SoC (AP SoC).
Editor's Note: This article first appeared on All Programmable Planet (APP), which was a thriving community website devoted to all things programmable. Sadly, APP is no longer with us, but many friendships were forged there that will last for years to come.
As I'm sure you will recall, the Zynq itself combines a full hard core implementation of a dual ARM Cortex-A9 microcontroller subsystem (running at up to 1GHz and including floating-point engines, on-chip cache, counters, timers, etc.), coupled with a wide range of hard core interface functions (SPI, I2C, CAN, etc.), and a hard core dynamic memory controller, all augmented with a large quantity of traditional programmable fabric, some programmable analog functionality, and a substantial number of general-purpose input/output (GPIO) pins. In addition to the Zynq, the ZedBoard contains everything necessary to create a Linux, Android, Windows, or other OS/RTOS-based design. Additionally, several expansion connectors expose the processing system and programmable logic I/Os for easy user access.
Hurray! My ZedBoard has arrived!
For my first blogs about the Zynq, I thought would write a simple guide explaining how the design tools integrate and what is needed to get the board up and running with a simple application that can be built upon in both software and hardware terms.
What? They expect me to read the instructions first?
Creating an All Programmable SoC design requires a little more effort than developing a traditional logic-based FPGA design; however, it is still pretty straightforward and the tool chain provides good guidance. To create an All Programmable SoC design, you will need to use, as a minimum, the following:
- Xilinx Platform Studio: This is where you create you processing system, be it a PowerPC, Microblaze, or -- in this case -- the Zynq's dual core ARM Cortex-A9. Here you define the configuration, interfaces, timing, and address ranges; everything needed to generate a processor system. The output from this process is an HDL netlist defining your system.
- Xilinx ISE: Most FPGA engineers are familiar with this tool, which takes your HDL design -- including the XPS netlist -- and generates the required BIT configuration file.
- Xilinx Software Development Kit (SDK): This is where the software that will run on the processing system is developed. To correctly generate the software, the SDK needs to be aware of the hardware configuration of the system.
- Impact: Performs the loading of the BIT configuration bitfile into the system.
All of these tools can be used in isolation to create an All Programmable SoC. Rather helpfully, however, Xilinx PlanAhead is capable of integrating them together, thereby allowing for a much simpler development process. It is using this PlanAhead approach that I will focus upon for the rest of this blog.
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